Computer Architecture: Intro Anatomy of a CPU

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Computer Architecture Intro Anatomy of a CPU

• J. Schmalzel
• S. Mandayam

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Objectives, 1

• ? Describe major functional elements of CISC,
  RISC architectures
• Perform detailed analysis and synthesis of
  combinatorial and sequential subsystems using
  schematic and/or behavioral design capture w/ sim
• Describe principles and applications of the three
  basic computing elements CPU, MEM, I/O
• Use an embedded system that includes diverse
  architectural features

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Objectives, 2

• ? Apply analytic and simulation techniques to
  predict and verify performance metrics
• ? Design an example architecture using SOTA tools
• Identify opportunities for hardware and software
  trade-offs
• (Insert your objectives here)
• ( and here)

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Hierarchical View of EP and Digital Systems
Operating System HLLs
Computer Architecture
State Machines
Interface Method
Design Techniques
MSI Functions
Boolean Algebra
Gates
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Central Processing Unit (CPU)

• Controls
• Executes
• Computes (Fixed- and/or Floating-Point)

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Example EP Feature List

• Small footprint
• 25.8 MHz CPU
• 40 CMOS-compatible parallel I/O lines
• Four CMOS-compatible serial ports max async rate
  of 806 kbps, max sync rate of 6.45 Mbps
• 8-bit data bus
• 13 address lines

• Control signals (I/O read, write)
• Master/slave config
• Reset input, output
• 5, 8-bit and 2, 10-bit timers
• 256K flash EPROM, 512KB SRAM
• RTC
• Status, WDT outputs

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Whats Implied by Feature List?

• Tight confederation of functional elements
• Ability to control and sequence operations
• Well-defined interfaces to external memory and
  I/O
• A sample EP architecture looks like

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BlockDiagram
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What about the CPU?

• The previous block diagram emphasized the
  collection of I/O and control resources
• One step closer on the abstraction scale is to
  look at the programmers model of the CPU

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CPU Register Set (Programmers Model)
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Internal CPU Architecture

• Program Counter
• Address Unit
• Instruction Register
• Instruction Decoder
• Register File
• Control/Timing
• Function Unit (ALU)

• Floating Point Unit (FPU)
• Status Register
• Stack Register
• Index Register

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Concept of CPU as Two Paths

• Data Path
• Where data elements flow from/to
• Where operations are performed
• Control Path
• The source of data path control

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Simple Model Data Path (7-18)
Dbus
W
n-bit bus
Register File
Dadd
Signal
Aadd
Const
MBsel
MuxB
Aout
Dout
FS
Function Unit
Status
Din
MDsel
MuxD
Dbus
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Instruction Word
DA AA BA MB
FS MD RW
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Instruction Set

• The way the EP computes and performs operations
• Load registers
• Immediate
• Memory
• Indexed
• Register-to-Register
• Exchange Registers
• Stack Operations
• 8- and 16-bit Arithmetic and Logical Operations
• Bit Set, Reset, Test
• Increment/Decrement

• Shifts and Rotate
• Block Moves
• Program Flow Control
• Fast A Instructions
• Control
• Privileged Instructions
• Miscellaneous (e.g. NOP)

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Questions, Comments, Discussion