Views

1
Views

• LRM Discipline Resolution
• Statement / Misconceptions
• Ports and net declarations take priority
• What the LRM states
• Priority is defined by the following
• Domain / Discipline of primitives and behavioral
  nets
• Domain / Discipline of declared nets throughout
  hierarchy
• Resolution of remaining nets via LRM or custom
  resolution methods
• Ports have nothing to do with net resolution,
  only insertion and direction of CM
• Clearly a few places were missed in the cleanup
  effort to clarify this about ports (8.2.3)

2
What Happens Here?
1) Assumption resistors are primitives thus
disciplines currently default to electrical 2)
Assumption digital buffer is a module and thus
has a port and the internal vpiLoConn is either
defined as a digital discipline (logic) or is
connected to digital behavioral code or digital
wire type and is thus is discrete domain (per LRM
3.4.3.3). 2a) If the assumption in 2 is false and
the buffer is a digital primitive then this is
currently an error per the LRM -1364 defines
that digital primitives have no port names and in
essence no ports (needed also for unique
names) -Verilog-AMS requires knowing the
discipline of the vpiLoConn of this missing
port -We originally had a section that named
these ports but the majority of the committee
voted to drop them, if we desire to support
this then this would needed to be added back and
any issues addressed 3) Best to look at this in
another view ACTION ADD Definition of SPICE
primitives to LRM, ADD Digital port names back?
3
Another view of the question
Look first only at discipline resolution Default
method (LRM 8.4.4.1) propagate all disciplines
up hierarchy, analog wins! - Net A resolves to
electrical from res, Net C resolves to electrical
from Net A, Net E resolves to logic from buf,
Net B resolves to electrical from res, Net D
resolves to electrical as analog wins Detail
method (LRM 8.4.4.2) analog propagates up and
down hierarchy, stops at digital - Propagate up
Net A resolves to electrical from res, Net C
resolves to electrical from Net A, Net D
resolves to electrical from Net C, Net E
cannot resolve in the propagate up mode, Net B
resolves to electrical from res - Propagate
down Net E resolves to electrical from Net D
4
Where are the CMs
Connect Modules
D
vpiUpConn
vpiLoConn
C
E
B
vpiUpConn
vpiLoConn
res
buf
A
vpiUpConn
vpiLoConn
res
Default Resolution
Detail (Alt) Resolution
Note, in this simple design - Default and
Detail result in the same answer (just which port
to insert CM on) - connect_mode argument has no
effect since only one digital component
5
In the LRM, what is a Primitive?

• Leaf levels in the hierarchy
• This includes
• SPICE primitives
• Ports connected to analog or digital behavioral
  code
• Ports connected to digital continuous assignments
• Ports connected to digital primitives (pseudo
  functions)
• Are mixed cells (structure and behavior) a
  problem for the LRM?
• No
• Lets examine the possibilities

6
Mixed Cells

• Analog behavioral and analog primitives
• module foo (out)
• inout out
• electrical out, gnd // REQUIRED DUE TO ANALOG
  BEHAVIORAL ACCESS
• ground gnd
• capacitor (.c(10p)) cout (out, gnd)
• analog begin
• V(out) lt sin(abstime)
• end
• endmodule
• What is the discipline of out? electrical!
• Analog behavioral code required defining
  discipline!

7
Mixed Cells

• Digital behavioral/assigns and digital
  primitives
• module foo (outa, outb)
• output outa, outb
• reg outb wire outa
• buf b1 (outa , bx1 )
• buf b2 (outb , bx2)
• assign outa 1
• initial begin
• outb 0
• 5 outb 1
• 10 outb 1
• end
• endmodule
• What is the disciplines of outa and outb? Empty
  discipline with a domain binding of discrete.
  Pick up discipline from default_discipline if
  needed (see 3.4.3.3.)

8
Mixed Cells

• Analog behavioral and digital primitives
• module foo (out) // Really a mixed port but
  resolution removes this issue
• output out
• electrical out
• buf b1 (out ,bx1 ) // currently illegal to have
  digital prim connected to analog net!
• analog begin
• V(out) lt sin(abstime)
• end
• endmodule
• What is the disciplines of out?
• This is illegal today according to the LRM!
• If this were made to be legal again then out
  would be electrical
• CM would be inserted across port of buffer

9
Mixed Cells

• Analog primitives and digital primitives
• module foo (bx1,out)
• input in output out
• electrical gnd ground gnd
• buf b1 (out , bx1) // currently illegal to have
  digital prim connected to analog net!
• capacitor (.c(100p)) cout(out, gnd)
• endmodule
• What is the disciplines of out?
• This is illegal today according to the LRM!
• If this were made to be legal again then out
  would resolve to electrical and CM would be
  inserted across port of buffer
• You could declare net to be digital then CM is
  across analog port

10
Mixed Cells

• Digital behavioral and analog primitives
• module foo (out)
• output out
• electrical gnd ground gnd
• capacitor (.c(100p) c1 (out, gnd)
• initial begin
• out 1
• 5 out 0
• 10 out 1
• end
• endmodule
• What is the disciplines of out? Empty discipline
  with a domain binding of discrete. Pick up
  discipline from default_discipline if needed (see
  3.4.3.3.)
• CM would be inserted across port of capacitor
  (form of coercion)

11
Mixed Cells

• Digital behavior/assign and analog behavior
• module foo (out)
• output out
• electrical out
• initial begin
• out 1
• 5 out 0
• 10 out 1
• end
• analog V(out) lt sin(abstime)
• endmodule
• What is the disciplines of out?
• This is illegal per the LRM (sections 3, 7, and 8
  multiple places)
• This is was behavioral interaction is for! See
  LRM 8.3

12
Connect Module Overview

• Auto Insertion consists of the following
• Connect modules to define the behavioral at the
  interface
• Discipline Resolution to define the disciplines
  of the undeclared interconnect
• Connectrules to define which connectmodules (CM)
  to use and their attributes
• Global parameter settings
• Individual parameter settings
• Hierarchical segregation of ports (split /
  merged)
• Driver / Receiver segregation of all mixed nets
• Auto Insertion of CM based on above information

13
Connectmodule (LRM sec. 8.5, 8.6)

• Special version of a Verilog-AMS module that are
  used in the conversion between discrete and
  continuous signals
• Full power of Verilog-AMS language
• Only allowed two ports (one discrete, one
  continuous)
• Direction limited to following pairs
• continuous discrete type
• input output a2d
• output input d2a
• inout inout bidir
• Direction and discipline of ports define
  connectmodule type
• Support special driver access functions for
  accurate modeling
• Special ability to model analog effects on
  digital nets

14
Discipline Resolution (LRM section 8.4)

• Resolves undeclared interconnect to a specific
  discipline
• Extremely useful in structural netlist to not
  declare the discipline of interconnect
• Allows selected views in hierarchy to define the
  discipline and influence CM insertion
• Resolves specification of undeclared nets when
  multiple compatible disciplines are available
• Two defined methods to control resolution
• Influences where connect modules (CMs) are
  placed in hierarchy
• Methods can be coerced to control methods (IP
  pre-characterized block)

15
Connect Rules (LRM sec. 8.7, 8.8)

• Unidirectional and bi-directional automatic
  insertion of connection modules between
  incompatible domains
• All nets in the design are resolved to a single
  discipline throughout the hierarchy per the
  discipline resolution method selected
• Connect modules are selected based on the port
  direction being connected to and the disciplines
  on both sides of that port (vpiLoConn, vpiHiConn)
  using the first rule to match
• General parameter passing defined with connect
  rule
• Ability to override the defaults of the connect
  module

16
Auto Insertion

• The connect statements define global connection
  rules that apply to the entire design
• The simulator is responsible to insert the
  connection modules (IEs) as specified by the
  global rules during design elaboration
• Additional connect_mode attribute to direct the
  segmentation of the net at each level of the
  hierarchy specified on connect statement

17
Discipline Resolution
18
Default Discipline Resolution
A
A

• Single Bottom Up Traversal
• Disciplines Propagate Up
• Analog wins conflicts

D
B
A
C
D
D
A
E
D
F
19
Detailed Discipline Resolution

• Analog Propagates Up and Down!
• Digital fortresses, blocks analog
• Bottom Up Traversal
• Top Down Traversal
• Repeat until Resolved

A
A
A
B
A
C
D
D
A
E
D
F
20
Automatic CM Insertion
Default Discipline Resolution

• Fewer Connect Modules
• Higher in Hierarchy
• Less Modeling of Analog
• Faster
• Less Accurate
• Tradeoff!

A
A
D
B
A
C
D
D
A
E
D
F
21
Automatic CM Insertion
Detailed Discipline Resolution
A
A

• More Connect Modules
• Lower in Hierarchy
• More Modeling of Analog
• Slower
• More Accurate
• Tradeoff!

A
B
A
C
D
D
A
E
D
F
22
Discipline Resolution Tree
Net out
Port Unresolved Net
D
A
A
D
D
D
D
D
Leaf primitives
A
A
D
A
D
D
D
D
A
A
D
D
D
A
D
23
Details

• The following slides show some of the details of
  connect modules, connectrules, and discipline
  resolution
• The language is very powerful and the following
  slide will aid you in taking full advantage of
  the language

24
Discipline Resolution

• A few more issues
• What happens if disciplines being passed up are
  compatible but different (e.g. cmos1, cmos2,
  cmos3)
• Special connect statements allow selection or
  which one wins connect cmos1 cmos2 cmos3
  resolveto cmos1
• Non-compatible disciplines connected to the same
  net are illegal
• What happens if I force a net to a specific
  discipline (coercion)?
• No resolution is needed (typically done for IP to
  prevent resolution into IP)
• Can be done with OOMR discipline declaration
• cmos1 top.I1.I2.I3.I4.clk

25
Auto Insertion

• Where do CM get placed?
• Remember all nets have been resolved
• Across a port and a net, thus the port direction
  of the port selects which CM

top
electrical
Port direction for I2, and disciplines of the
upper and lower connections determines which
connect rule matches Without coercion the port
will always be a digital port
I1
electrical
I2
I1
top
I2
logic
26
Connectrule Connect Mode

• Supports connect_mode attribute to direct the
  segmentation of the net
• Allows a refined IE insertion when there is more
  than one port on a net (for each level of
  hierarchy) for which the connect statement
  applies
• Example
• connect e2c split
• connect e2c merged
• Default mode is merged

V
27
Connectrule Parameter Overrides

• Supports customizing of auto-inserted connect
  module by changing parameters of parameterized
  connection modules
• Use same connect module for multiple technologies
• Can set parameters of auto-inserted connections
  on an instance by instance basis by use of the
  defparam statement
• necessitates predictable instance name rules for
  the auto inserted modules (described in the LRM
  8.8.5)
• Examples connect e2c merged (.vcc(3.3))
  // effects all uses of this statement
• defparam input__e2c__logic.vcc 2.5 //
  overrides specific instance of connect module
• UpperSignalName__connectmoduleName__LowerDisciplin
  e

28
Connectrule Statements

• Connect Specification Statements
• connectrules process_cmos1
• // specified module determines IE type based
  on port directions
• // A2D module ports analog in, digital out,
  override parameter r
• connect cmos1_a2d split (.r(30K))
• // D2A module ports analog out, digital in
• connect cmos1_d2a
• // BiDir module ports analog inout, digital
  inout
• connect cmos1_bidir
• // override disciplines specified inside of
  connect module
• connect cmos1_d2a_detail input cmos2 output
  electrical
• // discipline resolution
• connect cmos1 cmos2 resolveto cmos1
• endconnectrules

29
Connectrule Rule override

• Verilog-AMS provides the ability to explicitly
  state the type of the connect module being
  specified or override its type.
• Supports the overriding of direction and/or
  disciplines (compatible) in a connect module
• Allows use of same connect module for multiple
  technologies
• Aids library based designs by eliminating need to
  search entire library (just use the ones
  specified by the statement)
• Example connect e2c (.vcc(3.3)) output
  cmos2 input electrical
• connect e2c (. vcc(2.5)) inout cmos2 inout
  electrical

30
Connect Module Finite Output Impedance

• connectmodule d2a(d,a)
• input d output a
• logic d electrical a, n // intermediate node
• parameters rout1 real out
• analog begin
• _at_(posedge(d)) out 5.0 // or 3.3
• _at_(negedge(d)) out 0.0
• // drive intermediate node
• V(n) lt transition(out,3n,3n)
• // resistive output, rout
• I(a,n) lt V(n) / rout
• end
• endmodule

31
Digital Islands, why?

• This is an interesting question as it is not
  stated why in the LRM, just that it exists!
• What are digital islands?
• A signal is a hierarchical collection of nets
  which because of ports (and OOMRs) are contiguous
  (8.2.3)
• Each net segment can have its own discipline
• All analog nets on a signal are connected to a
  signal analog node
• Contiguous digital nets of different disciplines
  are essentially islands
• Non-contiguous digital nets of the same
  discipline due to other discipline are digital
  islands
• Maybe a picture will help?

32
Digital Islands
The signal go through several levels of hierarchy
and is made up of multiple net segments Each net
segment has discipline defined for it Either
logic3v, logic5v, or electrical (analog) The net
segments of I1, I11, and I111 are contiguous and
a single island. Since net I11 is of a different
digital discipline but not connected to analog it
becomes mute as it is compatible with the net in
I1 The net segment in I2 is a separate island due
to a different domain and it is not
contiguous The net segment in I222 while the same
discipline as in I1, I11, and I111 is not
contiguous with those segments and is thus a
separate digital island The net segment in Top
and I22 are not contiguous but are analog and
thus resolve to one node
33
Digital Islands
What does this mean? - Electrical nodes on this
signal always have the same value - Values of the
nets on I1, I11 and I111 are resolved by the
digital solver - Value on I2 is resolved as a
separate net by the digital solver - Value on
I222 is resolved as a separate net by the digital
solver - Connect modules are put on the ports of
I1, I2, I22, and I222
34
Digital Islands LRM view
Hierarchical Representation
Internal Representation
receiver(s)
receiver(s)
connect driver
logic5v
logic3v
connect receiver
connect driver
driver(s)
receiver(s)
logic3v
electrical
receiver(s)
Why the above picture? (This picture has been in
LRM from day 1) This picture leads into the
driver receiver segregation issues It also points
out that there is only one analog node per
signal It also points out that connect modules
are inserted hierarchically It also shows how
digital islands are viewed internally
driver(s)
35
Digital Island, is it needed?

• Well back to the big question, why digital
  island?
• This is not what hardware does is it?
• Can a single digital net have two different
  values?
• Lets examine Verilog first
• All nets resolve to a single value via simulator
  resolution (strengths, wire types)
• The resolved value is an estimate of hardware
• Hardware looks more like analog
• Only matters on mixed nets, digital only nets not
  effected
• Do digital islands make analog results less
  accurate?

36
Digital Islands
In3a is with digital islands, in3b is without
digital islands Is digital really correct when
looking it from an analog perspective? If digital
islands are not needed then why do we ever need
split? Note, with driver update one could also
mimic this type of behavior Relying on digital
to provide a unified value will result in less
accurate analog values!
R1
R2
R4