Lec 11 Flip Flop Excitation Tables

1
Lec 11Flip Flop Excitation Tables
CSCE 211 Digital Design

• Topics
• Sequential Circuits
• SR Latch
• Clocked SR
• Master Slave
• Master Slave VHDL
• Readings 5.4, 5.9, 5.10, 4.4

October 13, 2009
2
Overview

• Last Time
• Sequential Circuits Basic Nor Latch (really time
  before)
• Clocked SR flip flops
• Master Slave SR
• Test 1 discussion (due Take home portions due
  Today)
• New
• Sequential Circuits
• Clocked SR flip flops
• Master Slave SR
• VHDL two bit adder
• VHDL
• Structural specifications

3
Clocked SR-Latch
S1
R1

• Toms Link
• http//www.play-hookey.com/digital/jk_nand_flip-fl
  op.html

4
Clocked SR-Latch Implementation
S
Q
CP
Qbar
R
74LS00
5
74 LS10
6
74LS49 Seven segment display driver

• 74LS49/74LS47
• Inputs BCD digit (DCBA) (D is the MSB)
• Outputs abcdefg the seven segment driver lines
• Schematic fig 5-45
• Note negation of inputs to or-gate
• x y (x y) (x . y) (x .
  y)
• Its a NAND!
• Truth table fig 5-21

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HW Create VHDL Module for Seven Segment

• Using Xilinx Navigator create a VHDL module for
  the 74LS47 seven segment display driver
• Do VHDL for Dual 4-to-1 Mux
• Turn the MUX and Seven segment display modules
  into symbols
• Use them in schematic diagram connecting four
  2-bit input numbers (base 4) and pass them
  through the Mux to the seven segment driver. We
  can then use the select lines to choose which
  number is routed through.

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HW Develop circuit

• Using the switch to set the values of the four
  base-4 numbers and route the output to the MUX.
• From the MUX extend with 00 to make a BCD number
  that is sent to the input of the seven segment
  display driver.
• The hook this up to the seven segment display.

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Hints on Circuit

• Hook up MUX ?BCD-to-7Seg ? 7Segment
• Steps
• 1. Vcc,GND to all
• 2. put 330 ohm resistors in series with anode
  connections to LSD5061-11 (MAN71A) hooking them
  to Vcc
• 3. Test the 7-segment display hooking the
  individual cathodes to GND
• 4. Hook up outputs from 74LS47 to cathode inputs
  of 7-segment display
• 5. Hook the LampTest (pin 3) of the 74LS47 to
  GND, all segments should light up.
• 6. Hook up A1,A0 inputs of 74LS47 to Mux outputs,
  A2 and A3 should be GND
• 7. Test various values of select lines and mux
  inputs

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Pins of Seven Segment Display Digit LSD5061-11
e d c b a f g
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MAN71 (In last years Kit)
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74LS47 BCD to Seven Seg. Driver
13
74LS153 Dual 4 input MUX
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Hooking them Up
74LS153
74LS47
74LS153
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Hand-In Summary

• VHDL of seven segment driver 74LS47
• Structural Drawing of hook up of Mux to
  SevenSegmentDriver to seven segment display.
• Later Protoboard Circuit implementation of this
  circuit including
• The switch for setting the four base-4 numbers.
  These must be set so that positions 1 and 2 are
  one two bit number, positions 3 and 4 another etc.

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Transition Table for Clocked SR flip-flop
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J-K Flip Flop
J K
http//www.play-hookey.com/digital/jk_nand_flip-fl
op.html
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Transition Table for JK Flip Flop
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The D Flip Flop

• One input D
• D 0 ? Q(t1) 0
• D 1 ? Q(t1) 1

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The T Flip Flop

• One input T
• T 0 ? No change Q(t1) Q(t)
• T 1 ? Complement Q(t1) Q(t)

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Excitation Tables

• What inputs do we need to supply to the flip-flop
  do achieve the desired state transition?

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Excitation Tables JK

• What inputs do we need to supply to the flip-flop
  do achieve the desired state transition?

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Excitation Tables T

• What inputs do we need to supply to the flip-flop
  do achieve the desired state transition?

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Characteristic Equations

• Next state as a function of current state and
  inputs
• Q F(Q, S, R) // Q Q(t1)
• Table 7-1 of text
• For MS S-R flip-flop Q

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Characteristic Tables and Equations

• Characteristic Tables for a flip flop
• Describes next state Q or Q(t1) as function
  of inputs and in terms of current state Q or
  Q(t)
• Characteristic Equation specifies the next state
  as a function of current state and inputs (as an
  equation)

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Table 7-1 Characteristic Equations
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Excitation Tables

• What inputs need to be given to cause a specific
  state transition?

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VHDL SR latch

• Table 7-36 page 642 SR Latch in VHDL

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Edge Triggered D Flip-Flops

• Positive edge triggered

master
slave
QM
D Q C
D Q C
D
CLK
Suppose D0 for sometime then Qm 0 and Q
0 Then tracing this through setting D1,
CLK1 The master changes when the clock CLK goes
to 0 This means QM goes to 1, and then when the
CLK goes to 1 Q becomes 1
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Edge Triggered D Flip-Flops with Enable

• Positive edge triggered with enable

master
slave
D Q C Q
D
CLK
Tracing this through setting D1, CLK1 The
master changes when the clock CLK goes to 0
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74LS74 Commercial edge triggered D
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VHDL Edge triggered D

• Table 7-37 page 643 edge triggered D in
  Behavioral VHDL Note Glitches in figure All ?
  Should be

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Clock Generator

• Table 7-39 p 644

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State-machine structure (Mealy)
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State-machine structure (Moore)
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TBird Lights

• State machine problem

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TBird Lights