332:479 Concepts in VLSI Design Lecture 8 DC

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332479 Concepts in VLSIDesignLecture 8 DC
Transient Response

• David Harris and Michael Bushnell
• Harvey Mudd College and Rutgers University
• Spring 2004

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Outline

• DC Response
• Logic Levels and Noise Margins
• Transient Response
• Delay Estimation
• Inverter Voltage Transfer Characteristics
• Static Load and Pseudo-nMOS Devices
• Transmission Gates and Tri-state Inverter
• Summary

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Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

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Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

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DC Response

• DC Response Vout vs. Vin for a gate
• Ex Inverter
• When Vin 0 -gt Vout VDD
• When Vin VDD -gt Vout 0
• In between, Vout depends on
• transistor size and current
• By KCL, must settle such that
• Idsn Idsp
• We could solve equations
• But graphical solution gives more insight

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Transistor Operation

• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?

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nMOS Operation
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nMOS Operation
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nMOS Operation
Vgsn Vin Vdsn Vout
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nMOS Operation
Vgsn Vin Vdsn Vout
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pMOS Operation
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pMOS Operation
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pMOS Operation
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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pMOS Operation
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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CMOS Inverter Switching

• Procedure to graphically get transfer
  characteristic
• Reflect p device characteristic about x-axis
• Take absolute value of p device characteristic
• Superimpose 2 characteristics
• Solve for common points of Vgs intersection
• Vinn Vinp, Idsn Idsp
• Switching point VDD / 2

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I-V Characteristics

• Make pMOS is wider than nMOS such that bn bp

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Current vs. Vout, Vin
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Load Line Analysis

• For a given Vin
• Plot Idsn, Idsp vs. Vout
• Vout must be where currents are equal in

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Load Line Analysis

• Vin 0

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Load Line Analysis

• Vin 0.2VDD

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Load Line Analysis

• Vin 0.4VDD

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Load Line Analysis

• Vin 0.6VDD

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Load Line Analysis

• Vin 0.8VDD

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Load Line Analysis

• Vin VDD

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Load Line Summary
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DC Transfer Curve

• Transcribe points onto Vin vs. Vout plot

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Operating Regions

• Revisit transistor operating regions

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Operating Regions

• Revisit transistor operating regions

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Five Regions of Operation

• Transition both transistors on short current
  pulse drawn from supply
• A 0 Vin Vtn, n cutoff, p linear, Vout
  VDD
• B Vtn Vin lt VDD / 2, p linear, n
  saturated
• For n, Vgs Vin
• Idsn bn Vin Vtn 2
• 2
• For p, Vgs Vin VDD Vds (Vout - VDD)
• Idsp - bp (Vin VDD Vtp) (Vout VDD)
  (Vout VDD)2
• 
  2

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Regions of Operation

• Let Idsp - Idsn, and then
• Vout
• (VinVtp) (VinVtp)2 2(Vin- - Vtp)
  VDD bn (Vin Vtn)2
• 
  bp
• C Both n and p devices saturated unstable
• 2 current sources in series
• Idsp - ½ bp (Vin VDD Vtp)2
• Idsn ½ bn (Vin - Vtn)2

VDD 2
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Regions of Operation

• With Idsp - Idsn,
• Vin VDD Vtp Vtn
• 1
• If bn bp and Vtn - Vtp, you get Vin VDD/2
• Can have Vin Vtn lt Vout lt Vin Vtp when Vin
  VDD/2
• Non-ideal current source behavior
• Slight slope due to channel length modulation

bn bp
bn bp
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Inverter Behavior

• Very steep transition between logic 1 and 0
• Highly desirable
• Small Vin change causes big Vout change
• Much better than nMOS inverter
• Logic gate threshold Vinv point where Vin Vout

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Regions of Operation

• D p in saturation, n in linear region
• VDD/2 lt Vin VDD Vtp
• Idsp - ½ bp (Vin VDD Vtp)2
• Idsn bn (Vin Vtn) Vout - ½ Vout2
• With Idsp - Idsn, then
• Vout (Vin Vtn) - (Vin Vtn)2 -
  (Vin VDD Vtp)2

bp bn
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Regions of Operation

• E Vin gt VDD Vtp, p device cut-off, n linear
• Vgsp Vin VDD, greater than Vtp so Vout 0

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Beta Ratio

• If bp / bn ? 1, switching point will move from
  VDD/2
• Called skewed gate
• Other gates collapse into equivalent inverter

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Beta Ratio Influence on Transfer Characteristic

• b a T-1.5 Ids a T-1.5
• Due to decreased m as T increases
• Gate threshold Vinv state where Vin Vout
• To change , must change channel L or W
• 1 is nice a capacitive load can charge
  
• discharge in equal
  times
• Equal current source sink capabilities

bn bp
bn bp
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Temperature Dependency
bn bp

• Since voltage transfer depends on
• So, it is roughly independent of T
• Vtn, Vtp decrease slightly as T increases
• Extent of Region A reduced
• Extent of Region E increased
• If T rises by 50 oC, Vtn Vtp each drop 200 mV
• 0.2 V shift in inverter threshold

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Noise Margins

• How much noise can a gate input see before it
  does not recognize the input?

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Logic Levels

• To maximize noise margins, select logic levels at

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Logic Levels

• To maximize noise margins, select logic levels at
  
• Unity gain point of DC transfer characteristic

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Noise Margins

• Desirable to have VIH VIL and at a value midway
  on logic swing from VOL to VOH
• Prefer to have NMH NML, but sometimes we
  compromise this for speed

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Transient Response

• DC analysis tells us Vout if Vin is constant
• Transient analysis tells us Vout(t) if Vin(t)
  changes
• Requires solving differential equations
• Input is usually considered to be a step or ramp
• From 0 to VDD or vice versa

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Delay Definitions

• tpdr
• tpdf
• tpd
• tr
• tf fall time

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Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise time
• From output crossing 0.2 VDD to 0.8 VDD
• tf fall time
• From output crossing 0.8 VDD to 0.2 VDD

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Delay Definitions

• tcdr rising contamination delay
• From input to rising output crossing VDD/2
• tcdf falling contamination delay
• From input to falling output crossing VDD/2
• tcd average contamination delay
• tpd (tcdr tcdf)/2

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Simulated Inverter Delay

• Solving differential equations by hand is too
  hard
• SPICE simulator solves the equations numerically
• Uses more accurate I-V models too!
• But simulations take time to write

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Delay Estimation

• We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask What if?
• The step response usually looks like a 1st order
  RC response with a decaying exponential.
• Use RC delay models to estimate delay
• C total capacitance on output node
• Use effective resistance R
• So that tpd RC
• Characterize transistors by finding their
  effective R
• Depends on average current as gate switches

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RC Delay Models

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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Elmore Delay

• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder

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Example 2-Input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

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Example 2-Input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-Input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-Input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-Input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-Input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-Input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Delay Components

• Delay has two parts
• Parasitic delay
• 6 or 7 RC
• Independent of load
• Effort delay
• 4h RC
• Proportional to load capacitance

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Contamination Delay

• Best-case (contamination) delay can be
  substantially less than propagation delay.
• Ex If both inputs fall simultaneously

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Diffusion Capacitance

• We assumed contacted diffusion on every s / d.
• Good layout minimizes diffusion area
• Ex NAND3 layout shares one diffusion contact
• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too

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Layout Comparison

• Which layout is better?

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Static Load CMOS Inverter

• Use resistor or current source both made from
  transistors
• Use static load inverters to
• Reduce of gate transistors
• Lower dynamic power usage

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Generic Static Load nMOS Inverter
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Pseudo nMOS Inverter

• Similar to depletion load in nMOS technology
• Bad for low-power applications, IDDQ testing
• Useful for high-speed applications, large fanin
  NOR gates
• To solve, use 2 cascaded pseudo-nMOS inverters
• n device saturated, p device linear

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Pseudo-nMOS Inverter DC Transfer Characteristic
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Pseudo-nMOS Equations

• Vgsn Vinv
• Idsn bn / 2 (Vinv Vtn)2, Vout gt Vin Vtn
• Let Vgsp - VDD
• Idsp bp (-VDD Vtp) (Vout VDD) (Vout
  VDD)2
• 
  2
• Equate 2 currents solve for Vout
• Vout - Vtp (VDD Vtp)2 C
• C k (Vin Vtn)2, k

bn bp
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Pseudo-nMOS Equations

• bn (VDD Vtp)2 (Vout Vtp)2
• bp (Vin Vtn)2
• Set Vinv 0.5 VDD to get equal noise margins
• With Vinv 0.5 VDD, Vtn Vtp 0.2 VDD, VDD
  5 V,
• Get bn / bp 6
• Heavily used where n-rich circuit needed static
  ROMs and programmable logic arrays (PLAs)
• But PLAs are no longer used

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Cascaded Pseudo-nMOS
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Pseudo-nMOS Inverter

• pFET is constant current source load

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Transmission Gate

• n device
• Initially, VOUT VSS
• S 0 1
• Conducts charges CL to VDD Vtn (VDD)
• 
  (Body effect at VDD)
• p device
• Initially, VOUT VSS,
• --S 1 0
• Conducts charges CL to VDD
• But, when VIN VSS, VOUT VDD
• Discharges CL through p device until VOUT Vtp
  (VSS)
• Degraded transmission of Logic 0

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Transmission Gate

• Overall Behavior
• S 0 (--S 1) n p off
• VIN VSS VOUT Z
• VIN VDD VOUT Z
• C-switch turns on and transmits a logic 1 to CL

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Output Characteristic for Control Input Changing
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Transmission Gate Regions

• Region A n saturated, p saturated (Vout lt
  Vtp)
• Treat p as constant current source,
• n current varies quadratically with VOUT
• Region B n saturated, p linear (Vtp lt Vout
  lt VDD Vtn)
• Both currents vary linearly with VOUT
• Region C n off, p linear (VDD - Vtn
  Vout)
• p current varies linearly with VOUT
• C-switch acts like resistor both n p devices
  contribute to resistance

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Transmission Gate Output Characteristic

• For switched input changing

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Transmission Gate R
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Tristate Inverter
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Summary

• DC Response
• Logic Levels and Noise Margins
• Transient Response
• Delay Estimation
• Inverter Voltage Transfer Characteristics
• Static Load and Pseudo-nMOS Devices
• Transmission Gates and Tri-state Inverter