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SiLi Detector Development

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Similar spectra 250 V th. 2000 V. Array Technology. Germanium. One more. Si(Li) ... Depth of interaction affects time of charge collection. CMOS Electronics ... – PowerPoint PPT presentation

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Title: SiLi Detector Development


1
Si(Li) Detector Development Richard Kroeger Jim
Kurfess, Eric Grove, Neil Johnson, Bernard
Phlips, Mark Strickman Naval Research
Laboratory Ethan Hull, Paul Luke, Richard Pehl,
Craig Tindall Lawrence Berkeley National
Laboratory
2
Si(Li) Technical Challenge
Si(Li) cannot tolerate high-temperature
processing steps (annealing) used to fabricated
instrinsic silicon detectors
Develop segmentation technique (ultrasonic
machining) - or - Develop a-Si contacts (vapor
deposition contacts)
a-Ge contacts
3
LBNL Detectors at NRL
Two Si(Li) devices tested at NRL 3 mm thick,
5.5 cm active diameter
  • Detector I
  • First Si(Li) device
  • 2 D-segments Si(Li)
  • Detector II
  • Second Si(Li) device
  • 2-mm wide strip
  • 2-D segments

4
Detector I Results
Capacitance vs. Vbias 20 C
Leakage vs. Temperature
Leakage vs. Voltage
5
Detector I Results
-180 C D section of Detector I Vacuum cryostat
122 keV 2.6 keV 1000 V
60 keV 2.7 keV 2000 V
662 keV 3.3 keV 1000 V
Similar spectra 250 V th. 2000 V
6
Array Technology
Germanium
One more
Si(Li) alternative 6 float zone silicon largest
available resistivity 0.5-2 kW-cm considerably
less than required for intrinsic silicon 7 mm
thick 300 V bias, 10-12 mm possible 10x10 cm
devices
7
3D readout
Depth of interaction affects time of charge
collection
3D readout board under test
Lab test 122 keV in Ge det.
8
CMOS Electronics
  • 10-30 pF detector 3 pF, interconnect lt5 pF,
    strip capacitance 10-20 pF
  • lt236 e rms noise (2 keV FWHM)
  • Peak detect dynamic range from 4 K through 400 K
    electrons (1100)
  • 3-D readout via 10 ns timing TDC on each
  • A variety of implementations are under evaluation
    for fast timing
  • Latch an analog time signal
  • Latch a digital counter
  • Digitize full waveform on each channel

NOVAs RENA-1 CMOS RENA-2 specs (now under
development) could meet the ACT requirements for
timing and dynamic range.
9
Plans
  • Several new Si(Li) devices shall be produced this
    year by LBNL
  • Contact fabrication techniques shall be explored
  • Segmentation techniques shall be explored
  • Devices shall taken to the IUCF for radiation
    damage testing
  • NRL will test devices and develop system
    architecture
  • NRL will test segmented devices
  • Large stacked array mechanical and cooling design
    shall be evaluated
  • Readout electronics shall be developed
  • Simulations and trade studies
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