Toro

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Toro

• High Performance Servo Control and Data
  Acquisition

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Toro Block Diagram
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Toro
A/D 16x 250 ksps 16-bit D/A 16x 200 ksps
16-bit
DDS timebase
SyncLink
32-bits DIO
FIFOPort
6711 DSP 150 MHz
32 MB SDRAM
Analog Control FPGA
MDR 100 IO connector
Low Noise Power Supplies
32/64 PCI bus
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Toro Analog IO Features

• IO has been selected for servo control
  applications
• Low latency
• Simultaneous sampling
• A/D
• 16 channels, 16-bit, 250 kHz
• Input ranges /-10V, /-5V, /-1V, 0-10V
• Anti-alias filter 125 KHz bandwidth, 6 pole
  filter
• Differential inputs, gt1M ohm inputs

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Toro ADC Data
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Toro Analog IO Features

• DACs
• 16 simultaneous, 16-bit, 250 kHz DACs
• No update latency
• Very low glitch energy 8 nv-s
• Output smoothing filter 100 kHz break
  frequency 2 pole
• /-10 V output standard
• Calibration
• Calibrated at factory coefficients stored in ROM
• Real-time digital error correction
• On-card auto-cal cal anytime, anywhere

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Toro Servo Timing
The Toro manual has a dedicated chapter showing
servo controls
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Conejo

• DSP With 10 MSPS Data Acquisition and Signal
  Generation for PCI

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Conejo Block Diagram
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Conejo
A/D 4x 10 MSPS 14-bit D/A 4x 10 MSPS 14-bit
DDS timebase
SyncLink
32-bits DIO
FIFOPort
6711 DSP 150 MHz
32 MB SDRAM
Analog Control FPGA
Low Noise Power Supplies
SMB IO connectors
32/64 PCI bus
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Conejo Features

• A/D Channels
• 4 independent channels of 14-bit A/D _at_ 10 MSPS
• programmable input ranges /-2V, /-1V, /-200mV
• single-ended, 50 ohm SMB input
• 6 pole anti-alias filter, -3dB _at_ 5 MHz
• 70 MHz wide bandwidth front end ideal for
  undersampling
• DAC Channels
• 4 independent channels of 16-bit D/A _at_ 10 MSPS
• /-2V output range
• single-ended 50 Ohm SMB output

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Conejo ADC
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Conejo Data Rates

• Full rate on all channels is 160 MB/sec to memory
• 300 MB/sec FIFO interfaces
• Full rate to DSP memory is 54 bus loading
• DMA is imperative to guarantee performance!
• Full rate on all channels to PCI is not possible

DMA to mem 160 MB/s
A/D 4 ch _at_ 10MSPS
160 MB/s
PCI 264 MB/s max
D/A 4 ch _at_ 10MSPS
160 MB/s
160 MB/s
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Conejo Applications

• Materials testing (GBM customer)
• High speed stimulus-response measurement
• Finds defects in material
• Custom logic used to for high speed stimulus and
  capturing response
• RF power measuring for complex waveforms - CDMA,
  GSM
• etc.
• Data Acquisition
• Simultaneous A/Ds ideal for multiple input
  measurements
• ultrasonic measurements
• RADAR
• fast SONAR
• engine testing and analysis

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Delfin

• 32 channel , gt100 dB analog

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Delfin
A/Ds 32 channels 24-bit, 192 KHz
gt100 dB analog fidelity!
64 bits digital IO
Analog Filters Gain
DACs 6 channels 24-bit, 192 KHz
6711 DSP
Flexible DDS timebase
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Delfin Block Diagram
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Delfin A/D Features

• 32 independent channels of 24-bit A/D _at_ 192 ksps
• sigma-delta A/D for highest AC performance
• Software programmable input ranges /-10V, /-5V,
  /-1
• differential, high impedance inputs
• DC or AC coupled inputs
• 2 pole anti-alias filter
• -3dB _at_ 96 kHz
• custom filters available
• ESD and over-voltage protected inputs

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Delfin A/D Performance
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Delfin ADC Data
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Delfin D/A Features

• 6 independent channels of 24-bit D/A _at_ 192 ksps
• /-10V output range with programmable attenuation
• 2-pole output smoothing filter
• single-ended output
• FIFO has 300 MB/sec burst rate from DSP
• Independent control channel using McBSP
• Allows access to D/A controls without
  interrupting output streaming
• Controls D/A functions such as mute and
  attenuation
• ESD and overvoltage protected

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Delfin Applications

• SONAR
• high resolution, high dynamic range
• high channel count for SONAR hydrophone arrays
• DSP for pre-processing data and controlling
  acquisition
• Vibration Measurement
• Simultaneous A/Ds ideal for multiple measurements
• high SFDR allows accurate measurements

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Delfin Applications

• Audio
• professional quality sound recording and playback
• supports all standard audio rates
• output channels for playback
• Data logging
• data logging using ASnap

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Delfin Competiton
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Oruga

• 64 channel A/D with DSP for Industrial Control
  and Data Acquisition

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Oruga Block Diagram
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Oruga
64 bits digital IO
32 input channels with filters
Dual 3 MHz, 16-bit SAR A/Ds
FIFOPort
Programmable Gain
DSP core 6713 _at_ 225 MHz 32MB SDRAM
4 DAC channels at 250 kHz, 16-bit
Expansion for 32 channels
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Oruga Core Features

• C6713 DSP _at_ 225 MHz
• 32 MB of SDRAM
• 64 bits digital IO
• FIFOPort
• DDS timebase
• 3x Counters/timers in FPGA
• 32/64 bit 33 MHz PCI interface
• PCI busmastering and mailbox interfaces

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Oruga Analog Inputs

• 64 total channels
• Independent filters and gain control
• 2 A/Ds capable of up to 3 MHz at 16-bits
• Each A/D supports up to 32 channels
• Each A/D section is completely independent
• Clocks and triggers
• Data flow control
• Supports multi-rate
• Digital error correction in FPGA

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Oruga A/D Signal Chain
Input channels 0-15, 32-47
FPGA
Int
Filter F(s)
Mux 321
FIFO 512 x32
Error Correct
Channel Scanner
Gain 1,2,8
A/D 3MHz, 16-bit
Triggering
Input channels 16-31, 48-63
DSP Bus
Triggering
Filter F(s)
Mux 321
FIFO 512 x32
Error Correct
Channel Scanner
Gain 1,2,8
A/D 3MHz, 16-bit
Int

• Channels are grouped so that 32-channel card has
  16 channels per A/D - gives 80 ksps per channel
• Independent timebases, triggers and data flow

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Oruga A/D Features

• A/Ds are 3 MHz
• Per channel rate 3MHz / number of enabled
  channels
• Scan 32 channels per A/D at 3Mhz/32 93kHz
• A/D has channel scanner feature to allow any
  combination of channels to be used
• Scan is near simultaneous for minimal phase
  error from channel to channel
• 1K sample FIFOs arranged as 512x32

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Oruga A/D channel scanning
93 kHz
Sample n
Sample n1
time
Input 0
Input 1
Input 2
Sample
333 ns
Input 3

• Channel samples are 333 ns apart no matter what
  the sample rate is

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Oruga A/D Specifications

• DC
• Gain lt 5 LSB (lt0.01) initial calibration
• Offset lt5 LSB (lt 1.5mV for /-10V range)
  initial cal
• AC
• S/N gt92 dB, for 1kHz sine input
• SFDR gt 82 dB
• THD lt -80 dB
• Channel isolation
• gt90 dB for 1 kHz 20Vp-p input on adjacent channel

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Oruga A/D Performance
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Oruga DAC Features

• 4 channels of 250 kHz, 16-bit simultaneous DAC
• Ultra-low glitch energy 5 V-ns
• Low latency, good for servo controls
• Servo timebase mode may be used
• 2-pole output smoothing filter
• Digital error correction in FPGA
• 1K sample FIFO arranged as 512x32
• Specs
• DC gain and offset calibrated to 5 lsb
• AC S/N gt 80 dB, SFDR gt 82 dB, THD lt -80 dB

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Migrating from ADC64 to Oruga
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Migrating From ADC64 to Oruga

• Software rewrite required for newer processor and
  DSP BIOS
• Porting focused mainly on integrating
  applications with BIOS, not on performance issues
• Connector is different MDR 100 is more reliable
  and has better signal quality
• All channels are differential input ADC64 had
  single-ended or differential options
• Some uses of memory will require cache management
  using functions provided in Pismo Toolset

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Oruga Demo !!
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Lobo

• Flexible digital platform with DSP and FPGA

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Lobo Target Applications

• Digital waveform capture
• A/Ds up to and beyond 1 GHz
• Remote analog data capture and processing
• Digital pattern generation
• Digitally vector signal generation for
  software-defined radios
• IC testing
• Digital Radio processing
• FPGA for IF processing, DSP for baseband

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Lobo Block Diagram
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Lobo
DSP core 6713 _at_ 225 MHz 32MB SDRAM
FPGA Capture Memory DIMMs 1-4 GB each
3M-6M Gate Virtex2 FPGA
500 MHz IO site 160 IO (80 pairs) connect to
the FPGA
32/64 bit, 33MHz PCI Bus
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Lobo Features

• 6713 DSP with user-configurable FPGA for
  preprocessing and interfacing
• Matador DSP/PCI back-end
• 3-6M gate Virtex2 FPGA
• GigaFIFO - gigantic capture buffer of up to 8GB
• Capture/play digital data at rates up to 2GB/sec!
• IO module site is PMC size, but uses higher speed
  connectors
• 160 digital connections configurable as
  single-ended, LVDS or PECL

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Lobo FPGA Features

• Xilinx Virtex2 FPGA has many features for DSP and
  communications
• Embedded hardware multipliers
• Embedded RAM blocks configurable as FIFOs, dual
  port RAM, CAM
• High speed IO standards LVDS/PECL
• Massive 6 Mgates (120K logic blocks) size
• Framework is 10 of the logic
• gt300 MHz internal clock rates
• Large library of DSP/interface/processing
  functions
• Programmable in high-level VHDL
• Reconfigurable in the field, loads via PCI
  interface

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Lobo Logic Framework Input Data Path
8 LVDS pairs for triggering, clocks and flow
control
DDR SDRAM DIMM 1 to 8 GB
DDR SDRAM controller
Triggering
300 MB/sec burst transfers to/from DSP
32 LVDS data pairs at 300 MHz
GigaFIFO controller
Input FIFO
Output FIFO
DSP interface
Virtex2 FPGA
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Lobo Framework Logic Features

• Implements data capture/playback using very large
  GigaFIFO
• Up to 4 GB storage, up to 500 MHz input rate
• gigaFIFO is a virtual FIFO made using a DDR SDRAM
  DIMM and two small buffer FIFOs in logic
• Allows capture/playback of digital data via
  IOPORT LVDS/PECL/LVTTL IO standards

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What Can Lobo Do Right Out of the Box?

• Data Capture and Logging
• Logger application ASnap
• Capture up to 4GB of data at 300 MHz, then log to
  disk
• Plug in a remote A/D and capture its data
• Easily modifiable for DSP post-processing of the
  captured data
• Data pattern generation and playback
• Awave application
• Play out waveform buffers of up to 4GB in length
  at up to 300 MHz
• Plug in a remote D/A and drive out complex, high
  speed waveforms
• DSP generates data for playback so the
  application is easily modified to generate all
  types of output patterns

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Developing Logic for Lobo

• Framework Logic illustrates major functionality
• DDR SDRAM interfacing and control
• Efficient DSP interfacing and data flow control
• Clock management
• Full source provided in VHDL
• Users can implement custom logic by building on
  this Framework

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Lobo Logic Development

• Full simulation testbench provided in VHDL is the
  starting point for user application development
• Testbench shows complete data flow in both
  directions to/from the DSP
• Customers can quickly integrated their logic
  designs into Lobo and run test simulations

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Logic Loading and Debugging

• Logic debug uses Virtex2 JTAG port with Xilinx
  ChipScope
• Gives access to internal signals like a logic
  analyzer
• Speeds up debugging by reducing the need for
  recompilations
• Downloading to the logic is fast and simple using
  the Innovative download applet or as part of the
  host application

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Available Lobo IO modules

• TTL IO
• 32-bit input and output ports
• Single-ended LVTTL ports
• Speed is lt200 MHz input
• MDR 50 connectors
• LVDS
• 32-bit input and output ports
• LVDS differential pairs direct to the FPGA
• Speed is up to 300 MHz
• MDR 68 Connectors

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Lobo Competition
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Matador Accessories

• Cables
• MDR 100
• SMB-BMC
• FIFOPort Cable
• Breakout Boxes
• Screw Terminal
• BNC
• Adapter
• Rackmount IO
• Convenient
• Customizable

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Matador Cards Summary

• Best Technology
• Easy to use 671x DSPs
• World Class Analog IO
• Trigger and capture features for all types of
  applications
• Best Software
• DSP BIOS
• Pismo Toolset handles both DSP and host
• Best Flexibility
• Programmable DSP on-card
• Customizable FPGAs
• Best Value
• More channels, more memory, more computing power