A1261664107pNkhO

1
Reconfigurable Computing (EN2911X,
Fall07) Lecture 14 SystemC (2/3)
Prof. Sherief Reda Division of Engineering, Brown
University http//ic.engin.brown.edu
2
Ports

• Ports are the means through which modules
  communicate with other modules. There are three
  basic port types that inherent from sc_port
• Input ports for receiving data
• Output ports for sending out data
• Input/output ports which combine the two

• An input port must be of type sc_in which is a
  template SystemC class
• sc_in lt T gt portname declares a input port of
  type T
• example sc_in lt sc_uintlt5gt gt myinport
• special case sc_in_clk clkname declares an
  input port of type bool

3
Port types

• An output port must be of type sc_out which is a
  template SystemC class
• sc_out lt T gt portname declares a output port of
  type T
• example sc_in lt sc_uintlt5gt gt myinport
• Special sc_out_clk clkname declares an output
  port of type bool
• An input/output port must be of type sc_inout,
  which is a templatized primitive SystemC class
• sc_inout lt T gt portname declares a in/out port of
  type T
• example sc_inout lt sc_uintlt5gt gt myinport

4
Synthesizable operations associated with ports

• There are two operations associated with ports
  read and write.
• sc_inout ports can be written to and read from
• sc_in ports can only be read from
• sc_out ports can only be written to
• Examples
• sc_in lt T gt portname
• T thedata portname.read()
• sc_out lt T gt portname
• portname.write(data)

5
Port mapping

• Ports can be mapped in any order. If myModuleA is
  an object of class ModuleA
• myModuleA.a1(in1)
• myModuleA.a2(in2)
• myModuleB.b2(in3)
• myModuleB.b3(out1)

6
Hierarchical design

• A module may contain sub-module instances in its
  body to form hierarchy
• There are no restrictions on the level of the
  hierarchy

7
Hierarchical design
SC_MODULE(Top) sc_inltsc_uintlt8gt gt in1
sc_inltsc_uintlt8gt gt in2 sc_inltsc_uintlt8gt gt
in3 sc_outltsc_uintlt8gt gt out // module
instances ModuleA myModuleA ModuleB
myModuleB // signal declarations
signalltsc_uintlt8gt gt sig SC_CTOR(Top)

8
Processes

• Processes describe the parallel behavior of
  hardware systems. Processes execute concurrently.
  The code within a process, however, executes
  sequentially.
• Three types of SystemC processes
• SC_THREAD
• SC_THREAD (special )
• SC_METHOD
• Process declaration must exist within its module
  constructor. processs sensitivity to clock,
  resets and other signal ports are specified when
  the process is declared

SC_MODULE(my_module) sc_in_clk clock void
my_thread() SC_CTOR(my_module)
SC_THREAD (my_thread) sensitive ltlt
clock.pos()
9
Process body
The process body contains the implementation of
the process. Like C functions, it may be
defined within the module definition,
typically in a .h header file outside the
module, typically in a .cpp file
my_module.h
my_module.h
SC_MODULE (my_module) void my_method() ...
SC_MODULE (my_module) void my_method()
... ...
my_module.cpp
void my_modulemy_thread() ...
A thread process body within a module definition
A thread process body outside a module definition
10
SC_THREAD processes

• A thread is a process that is called only once
  and never gets called again after termination
  (unless with a global reset)
• The thread process body is composed of two stages
  separated by the wait() statement
• The synthesis stage of a thread process should be
  typically written as a non-terminating loop.
• wait() can be used in the synthesis part which
  suspends the thread and resumes upon an event
  from the threads associated clock edge

void my_thread() . // compile-time
initialization stage wait() .. //
run-time hardware synthesis stage
11
Thread mechanisms

• Any statements between two wait() statements will
  be constructed as combinational logic. These two
  examples creates the same logic

wait() c (a0xF0) gtgt 4) (b0x0F)ltlt4) wait(
)
wait() c (a0xF0) c c gtgt 4 d
(b0x0F) d d ltlt4 e cd wait()

• The synthesis stage runs when it receives the
  signal to which the process is sensitive. The
  thread may be sensitive to a positive edge or a
  negative edge but not both.
• All the values assigned to variables in the
  initialization stage must be resolvable at
  compile-time. They cant contain signal or port
  reads

12
Thread example
void my_modulerun() int a, b // end
of compile-time initialization stage wait()
// start of runtime synthesized hardware stage
a 1 // clock cycle 1 wait() a
a1 // clock cycle 2 b 5 //
clock cycle 2 wait() a b // clock
cycle 3 b b1 // clock cycle 3
wait() ..
13
SC_METHOD processes

• A method process can be used to model either
  synchronous or combinational hardware
• SC_METHOD process must not contain wait()
  statements and must always terminate
• A method must be sensitive to all the ports and
  signals it reads
• Executed every time a trigger or temporal event
  occurs.
• Each signal and port written to must be written
  to on every execution of the SC_METHOD

SC_MODULE(adder) sc_in ltsc_uint lt32gt gt in1
sc_in ltsc_uintlt32gt gt in2 sc_out ltsc_uintlt32gt gt
out public void add() out
in1.read()in2.read() SC_CTOR(adder)
SC_METHOD(add) sensitive ltlt in1 ltlt in2
14
Process sensitivity list

• A sensitivity list identifies which input ports
  and signals trigger execution of the code within
  a process.
• A process can read from and write to ports,
  internal signals, and internal variables.
  Processes use signals to communicate with each
  other. One process can cause another process to
  execute by assigning a new value to a signal that
  interconnects them.

SC_MODULE (my_module) void my_thread()
sc_port ltboolgt clock ... SC_CTOR (my_module)
SC_THREAD (my_thread) sensitiveltltclock.pos(
) ...
15
Synthesis and compilation flow
Rest of code (testbenches, SW code)
Synthesizable subset
Celoxica agility synthesizer
Verilog/edif
Visual C
SystemC library
Quartus II
executable
16
Using signals to communicate between processes
and modules
incr.h
SC_MODULE(incr) private sc_signal ltint
gt x int d8 public sc_in
ltsc_intlt18gt gt SW sc_out ltsc_uintlt7gt gt
HEX0 void runadd()
void display() public SC_CTOR(incr)
SC_METHOD(runadd)
sensitive ltlt SW SC_METHOD(display)
sensitive ltlt x
incr
17
Implementing the processes
void incrdisplay() int digit, i0
int tx sc_uintlt7gt hex
digitt10 if (digit 0) hex
64 else if (digit 1) hex 121 else
if (digit 2) hex 36 else if(digit 3)
hex 48 else if(digit 4) hex 25
else if(digit 5) hex 18 else
if(digit 6) hex 3 else if(digit 7)
hex 120 else if(digit 8) hex 0
else if(digit 9) hex 24 HEX0hex
incr
void adderrunadd() int y
ySW.read() xy1
18
Synthesis point ag_main
include ltsystemc.hgt include ltincr.hgt // void
ag_main() adder incr(incr")
Use the produced Verilog file from Celoxicas
Agility compiler with the Quartus II software
19
Testing and verifying your code in a C
development environment
SC_MODULE(tester) int x public sc_out
ltsc_intlt18gt gt SW sc_in ltsc_uintlt7gt gt HEX0
void run(void) wait() while(1) cout ltlt
"enter a number" ltlt endl cin gtgt x
SW.write(x) wait() cout ltlt "answer " ltlt
HEX0.read() SC_CTOR(tester)
SC_THREAD(run) sensitive ltlt HEX0
20
Simulation entry point sc_main
include ltiostreamgt include ltsystemc.hgt include
"adder.sc.h" using namespace std int sc_main(int
argc, char argv) sc_signal ltsc_intlt8gt gt
SW sc_signal ltsc_uintlt7gt gt HEX0 incr
incr1(incr1") tester test1("test")
ad1.SW(SW) ad1.HEX0(HEX0)
test1.SW(SW) test1.HEX0(HEX0)
sc_start() return 0
elaboration
execution
21
Launch your executable (simulator)
This time you are using the Visual C compiler
together with the SystemC library
Simulate your system by executing it on the
command prompt