Indium Phosphide and Related Materials Conference, 2005

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Indium Phosphide and Related Materials
Conference, 2005
In0.53Ga0.47As/InP Type-I DHBTs w/ 100 nm
collector 491 GHz f? and 415 GHz fmax
Zach Griffith, Mattias Dahlström, and Mark
Rodwell Department of Electrical and Computer
Engineering University of California, Santa
Barbara, CA, 93106-9560 Xiao-Ming, Dmitri
Loubychev, Ying Wu, Joel Fastenau, Amy W.K.
Liu 119 Technology Drive, Bethlehem, PA
18015 Now with IBM Microelectronics
Semiconductor Research and Development Essex
Junction, VT 05452 griffith_at_ece.ucsb.edu,
805-893-3273, 805-893-3262 fax
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Fast divider designdesign considerations
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Scaling Laws, Collector Current Density, Ccb
charging time
GaAsSb base
InGaAs base
Collector Depletion Layer Collapse
Collector Field Collapse (Kirk Effect)
Collector thickness150 nm
Collector capacitance charging time scales
linearly with collector thickness if J Jmax
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Key HBT Scaling Limit ? Emitter Resistance
ECL delay not well correlated with f? or fmax
Largest delay is charging Ccb
? Je ? 10 mA/?m2 needed for 200 GHz clock rate
Voltage drop of emitter resistance becomes
excessive RexIc ?exJe (15 ???m2) ? (10
mA/?m2) 150 mV ? considerable fraction of
?Vlogic ? 300 mV Degrades logic noise margin
? ?ex ? 7 ???m2 needed for 200 GHz clock rate
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InP HBTs Where is the heat generated?
Vbe 0.95 V, Vce 1.3 V

• Si has 21 better thermal conductivity compared
  to InP
• InP has 101 better thermal conductivity
  compared to InGaAs
• Ternary materials needed to remove conduction
  band discontinuity between In0.53Ga0.47As and InP
• minimum thickness required to remove barrier
  35 to 40 nm
• Low resistance ohmic contact to sub-collector
  neededsmall bandgap material preferred,
  In0.53Ga0.47As
• this InGaAs acts as a thermal barrier to the
  substrate, thermal resistance increases rapidly
• Continued thermal scaling required for
  increased Si/SiGe like integration levels

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Digital circuits towards 200 GHz clock rate
142 GHz latch from NNIN _at_ UCSB 150 GHz ICs from
UCSB/GSC/RSC 200 GHz is the next goal
underlying technology400-500 GHz InP transistors
1.3 ?m base-collector mesa
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DC and RF performance210nm collector for PAs
210 nm collector, 35 nm base
Average ? ? 21, VBR,CEO 6.9 V Emitter contact
(from RF extraction), Rcont 7.2 ???m2 Base
(from TLM) Rsheet 446 ?/sq, Rcont 6.1
???m2 Collector (from TLM) Rsheet 12.6 ?/sq,
Rcont 5.5 ???m2
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DC, RF performance150 nm collector, 47 nm
transition
Summary of device parameters Average ? ? 36,
VBR,CEO 5.1 V (Ic 50 ?A) Emitter contact
(from RF extraction), Rcont 10.1 ???m2 Base
(from TLM) Rsheet 564 ?/sq, Rcont 9.6
???m2 Collector (from TLM) Rsheet 11.9 ?/sq,
Rcont 5.4 ???m2
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Layer structure -- 100 nm collector DHBT, two B-C
grades
Thickness (nm) Material Doping cm-3 Description
5 In0.85Ga0.15As 5?1019 Si Emitter cap
---- InxGa1-xAs gt 4?1019 Si Emitter cap grading
20 In0.53Ga0.47As 4?1019 Si Emitter
80 InP 3?1019 Si Emitter
10 InP 1?1018 Si Emitter
40 InP 8?1017 Si Emitter
30 InGaAs 7-4?1019 C Base
15 / 10 In0.53Ga0.47 As 9?1016 Si Setback
24 / 12 InGaAs / InAlAs 9?1016 Si B-C Grade
3 InP 2.75 / 5.5?1018 Si Pulse doping
58 / 75 InP 9?1016 Si Collector
10 InP 1?1019 Si Sub Collector
8.5 In0.53Ga0.47 As 2?1019 Si Sub Collector
300 InP 2?1019 Si Sub Collector
Substrate SI InP

• Objective
• Thin collector and increase doping for
  increased JKirk
• Investigate Jmax before current blocking in the
  base-collector grade
• High f? device without significantly reducing
  fmax
• Thin InGaAs sub-collector contact layer from
  12.5 nm ? 8.5 nm for reduced ?JA
• And do this for
• Two different base-collector grades
• Proven effective grade w/ thinned setback
  region 42 nm transition
• Thinned grade where the setback and grade are
  halved and pulse doping modified 25 nm
  transition
• All remaining layers identical

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DC, RF performance100 nm collector, 42 nm
transition
Summary of device parameters Average ? ? 40,
VBR, CEO 3.1 V Emitter contact (from RF
extraction), Rcont ? 7.8 ???m2 Base (from TLM)
Rsheet 629 ?/sq, Rcont 6.2 ???m2 Collector
(from TLM) Rsheet 12.9 ?/sq, Rcont 4.0
???m2
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DC, RF performance100 nm collector, 25 nm
transition
Summary of device parameters Average ? ? 45,
VBR, CEO 3.1 V Emitter contact (from RF
extraction), Rcont 10.4 ???m2 Base (from TLM)
Rsheet 616 ?/sq, Rcont 3.8 ???m2 Collector
(from TLM) Rsheet 13.3 ?/sq, Rcont 5.8
???m2
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Small signal model150 nm vs 100 nm collector
42 / 25 nm transition
Ic 27.8 mA Vcb 0.4 V Aje 2.58 ?m2 f? 491
GHz fmax 415 GHz
Ic 13.2 mA Vcb 0.6 V Aje 2.58 ?m2 f? 391
GHz fmax 505 GHz
?ex ? 7.8 ???m2 ?c,base ? 6.2 ???m2
?ex ? 10.1 ???m2 ?c,base ? 9.6 ???m2
Device junction dimensions 0.6 ?m emitter, 4.3
?m length, 1.2 ?m base mesa width
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Experimental Measurement of Temperature Rise
Temperature rise calculated by measuring IC ,
?VCB and ?VBE
25 nm transition ?JA 2.9195 1.4154?Vcb (K/mW)
42 nm transition ?JA 2.3613 0.8056?Vcb (K/mW)
thermal feedback coefficient ? 8.35?10-4 V/K
at Je 5.8 mA/?m2
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Temperature rise of 42 nm and 25 nm transitions
Table 3 -- Thermal data, 42 nm transition Table 3 -- Thermal data, 42 nm transition Table 3 -- Thermal data, 42 nm transition
?JA 2.3613 0.8056?Vcb (K/mW) -- Ajbe 0.6 ? 4.3 ?m2 ?JA 2.3613 0.8056?Vcb (K/mW) -- Ajbe 0.6 ? 4.3 ?m2 ?JA 2.3613 0.8056?Vcb (K/mW) -- Ajbe 0.6 ? 4.3 ?m2
Vce (V) Je (mA/mm2) ?T (K)
2.5 9.61 242
2.5 7.40 179
2.0 14.49 271
2.0 13.66 253
2.0 12.36 226
1.11 18.41 153
1.37 10.30 105
Thermal data, 25 nm transition Thermal data, 25 nm transition Thermal data, 25 nm transition
?JA 2.9195 1.4154?Vcb (K/mW) -- Ajbe 0.6 ? 4.3 ?m2 ?JA 2.9195 1.4154?Vcb (K/mW) -- Ajbe 0.6 ? 4.3 ?m2 ?JA 2.9195 1.4154?Vcb (K/mW) -- Ajbe 0.6 ? 4.3 ?m2
Vce (V) Je (mA/mm2) ?T (K)
2.5 8.60 304
2.5 7.12 247
2.0 14.90 386
2.0 12.33 311
2.0 10.90 272
1.23 15.30 176
1.37 8.53 111
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Simulated band-diagram Vbe 0.9 V, Vcb 0.0 V
42 nm transition
25 nm transition
42 nm transition filled, 25 nm transition hollow
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Summary of published HBT performance
Updated May 9, 2005