AreaEfficient True OnePeriod Delay Jitter Measurement

1
Area-Efficient True One-Period Delay Jitter
Measurement

• Presenter Pin-Chong Chan

2
Outline

• Introduction
• Previous Work
• Proposed Concept And Scheme
• Experimental Results
• Conclusions

3
Jitter
waveform timing variation
4
Analysis on the One Period Delay
One-period sampler. (a) Circuit diagram.
(b)Timing diagram.
5
Analysis on the One-Period Delay
One-period delay circuit.
Proposed self-sampled VDL structure
6
Analysis on the One Period Delay
One period is truly delayed for every period.
7
Proposed Structure
Proposed cycle-to-cycle jitter measurement
structure.
8
Area-Effective True One Period Delay
Proposed TOP circuit.
9
Basic Concept of CSMD
10
Verifying Simulation of the TOP Circuit
11
Comparison of SMD CSMD
21
41
33
63
45
73
12
Vernier Delayline
13
Measurement (I)
1?T
1?T
1?T
0
0
0
00011...
1
1
1
14
Measurement (II)
1
1?T
1
0
1
0
00011
1?T
1?T
1
15
Multiplexing For Multi-Purpose Measurement
Layout of a Double Period Delayline.
16
Experimental Results
Chip Implementation of a TOPJ.
17
Experimental Results
measured result of the TOP circuit
18
Experimental Results
Comparisons
19
Conclusions and Future Work

• In this paper we develop a novel digital and
  area-efficient true one period delay jitter
  measurement.
• For a delayline-based TOP with 300 stages, more
  than 75 of area overhead can be reduced.
• From simulations and physical experiments, our
  design can be performed at an acceptable speed.
• The same concept with more than two rings for
  further reduction in area will be the future work.

20
Reference

• D. Derickson and M. Müller. Digital
  Communications Test and Measurement High-Speed
  Physical Layer Characterization. Prentice Hall,
  ISBN 0132209101, 2007.
• T. Saeki et al. A 2.5-ns Clock Access, 250-MHz,
  256-Mb SDRAM with Synchronous Mirror Delay. IEEE
  J. Solid-State Circuits, 31(11)16561665, Nov.
  1996.
• T. Saeki, H. Nakamura, and J. Shimizu. A 10-ps
  Jitter 2 Clock Cycle Lock Time CMOS Digital Clock
  Generator Based on an Interleaved Synchronous
  Mirror Delay Scheme. In Proc. Symp. VLSI
  Circuits, pp.109-110, 1997.
• T. Saeki. et al. A Direct-Skew-Detect
  Synchronous Mirror Delay for Application-Specific
  Integrated Circuits. IEEE J. Solid-State
  Circuits, 34(3)372-378, Mar. 1999.
• K. Sung et al. Low power clock generator based
  on area-reduced interleaved synchronous mirror
  delay. IEE Electronics Letters. pp.399-400,
  vol.38, Apr. 2002.
• K. Sung and L.-S. Kim. A High-Resolution
  Synchronous Mirror Delay Using Successive
  Approximation Register. IEEE J. Solid-State
  Circuits, 39(11)1997-2004, Nov. 2004.
• Y.-M. Wang and J.-S. Wang. A Low-Power
  Half-Delay-Line Fast Skew-Compensation Circuit.
  IEEE J. Solid-State Circuits, 39(6)906-918, June
  2004.
• S. Tabatabaei and A. Ivanov. High Resolution
  Time-To-Digital Converter. US Patent No.6754613,
  June 2004.
• C.-Y. Li, C.-Y. Chou, and T.-Y. Chang. A
  Self-Referred Clock Jitter Measurement Circuit in
  Wide Frequency Range. In Proc. IEEE 15th Asian
  Test Symp., pp.313-317, Nov. 2006.
• K.-H Cheng, C.-W Huang, and S.-Y Jiang.
  Self-sampled Vernier Delay Line for Built-in
  Clock Jitter Measurement. In Proc. IEEE Int'l
  Symp. on Circuits and Systems, pp.1591-1594, May
  2006.
• T.-C. Huang, G.-B. Chang and L. Li. Congruence
  Synchronous Mirror Delay. In Proc. IEEE Int'l
  Symp. on Circuits and Systems, pp.2184-2187, May
  2007.

21
The End
Thank you for your attentions !