The YArchitecture for OnChip Interconnect: Analysis and Methodology

1
The Y-Architecture for On-Chip Interconnect
Analysis and Methodology

• H. Chen, C.-K. Cheng, A. B. Kahng, I. Mandoiu,
  and Q. Wang
• UCSD CSE Department
• U. Connecticut CSE Department
• Work partially supported by Cadence Design
  Systems, Inc., the California MICRO program, the
  MARCO Gigascale Silicon Research Center,
  NSFMIP-9987678 and the Semiconductor Research
  Corporation.

2
Motivation

• Interconnect becomes precious on a chip
• Manhattan architecture (M-architecture)
• two preferred routing directions
• increases wirelength and decreases communication
  capability
• Non-Manhattan interconnect architectures
• expected to use routing resources more
  efficiently
• X-architecture
• four routing directions
• reduction in chip area, wirelength, vias and
  power consumption

3
The Y-Architecture

• Pervasive use of 0-, 120- and 240-degree oriented
  wires for on-chip interconnect
• Supporting design methodologies
• Convex die shapes
• Hexagonal power/ground and clock distribution
  networks
• Special via arrangement
• Potential advantages of the Y-architecture
• reduced wirelength
• increased communication bandwidth
• improved global interconnects clock and power
  distributions
• regular routing grids
• novel means of avoiding serious via blockage

4
Our Contribution

• Previous work
• Rostoker et al. LSI Logic patents
• Cheng et al. ICCD02 ASP-DAC03
• Our contribution more complete, technically
  in-depth analysis of key deployment and
  methodology issues associated with the
  Y-architecture

5
Outline

• Throughput Analysis
• Wirelength Reduction
• Y Clock Tree
• IR-Drop of Y Power Distribution
• Routability
• Manufacturing Issues

6
Outline

• Throughput Analysis
• throughput of square meshes with a communication
  model based on Rents rule
• about 20 throughput improvement over
  M-architecture for square chips, which is close
  to the X-architecture
• Wirelength Reduction
• Y Clock Tree
• IR-Drop of Y Power Distribution
• Routability
• Manufacturing Issues

7
Multi-Commodity Flow Model

• Communication resources are decomposed into a 2D
  array of slots
• Edge capacities correspond to the physical
  limitations of routing channel
• Every pair of nodes communicates with required
  demand
• All communications occur at the same time

8
Communication Graph

• 7 x 7 meshes with different interconnect
  architectures.

9
Throughput Metric

• Throughput max. fraction of communication
  demand simultaneously satisfied between every
  pair of nodes
• tightly related to routability
• describes communication capabilities
• Use provably good multi-commodity flow algorithm
  Garg-Koenemann98, Fleischer99, Albrecht00

10
Rentian Communication Demand

• Occupation probability Stroobandt et al. 1999
• the probability that a given pair of points will
  be connected in an optimal circuit placement
• indicates the probability of communication
  between pairs of nodes
• derived from Rents rule
• Rentian Communication Demand
• communication between two nodes decreases with
  distance as D 2p-4
• p Rent's exponent,
• D Euclidean distance between nodes

11
Experimental Setup

• Square meshes with nodes up to 289
• Total routing area same for all meshes
• Total communication demand
• at most 1.8 in difference
• Normalized throughput
• total communication demand
• dimension of meshes

12
Throughput (and Improvement vs. M-Architecture)
in Square Chips

• Y-architecture achieves average throughput
  improvement of 19.8
• X-architecture achieves average of 21.9
  improvement

13
Outline

• Throughput Analysis
• Wirelength Reduction
• routing-aware placement
• up to 6 wirelength improvement over
  M-architecture
• Y Clock Tree
• IR-Drop of Y Power Distribution
• Routability
• Manufacturing Issues

14
Y-Aware Placement and Routing

• Previous estimates
• study Steiner Minimum Tree (SMT) on randomly
  generated point-sets
• do not adequately address the effect of
  routing-aware placement on the overall wirelength
  improvement
• Manhattan vs. Y-aware placer
• Manhattan placer tends to align components
  either vertically or horizontally
• ? impairs WL improvement of Non-Manhattan
  routing
• Y-aware placer consider hexagonal wires during
  placement
• ? better placements of nets for Y-routing

15
WL Improvement for X- and Y- over M- PlaceRoute

• A simulated annealing placer
• objective minimum total routed wirelength (SMT
  estimation) with M-, X- and Y-routing
• Y-arch WL improvement up to 6
• X-arch WL improvement up to 11
• a reduction of about 5 over the Y-architecture
  at the cost of one more routing direction

16
Outline

• Throughput Analysis
• Wirelength Reduction
• Y Clock Tree
• better total wirelength compared to both H and X
  clock tree structures
• better path length compared to the H tree
• IR-Drop of Y Power Distribution
• Routability
• Manufacturing Issues

17
Symmetric Y Clock Tree

• H-tree
• clock terminals arranged in a symmetric fashion
• a hierarchy of H structures
• X-tree
• a hierarchy of X structures
• optimum path delay
• reduced total wirelength
• Y-tree
• distorted X-tree
• optimum total wirelength
• reduced path delay
• no superposed parallel wires

Y Clock Tree
18
Path Length and Total Wirelength of H-tree,
X-tree and Y-tree

• Source-sink path length of Y-tree
• 21.1 less than H-tree
• 11.5 more than X-tree
• Total wirelength of Y-tree
• 8.9 less than H-tree
• 3.4 less than X-tree

19
Outline

• Throughput Analysis
• Wirelength Reduction
• Y Clock Tree
• IR-Drop of Y Power Distribution
• analysis of single-level power mesh
• more than 5 improvement over square mesh
• SPICE simulation of hierarchical power mesh
• 8.6 less IR-drop than square mesh
• Routability
• Manufacturing Issues

20
Model of Power Network

• Hierarchy of mesh structures
• equal wire spacing and pitch at each layer
• adjacent metal layers connected at the crossing
  points
• Via resistance ignored
• C4 power pads evenly distributed on the top layer
• Uniform current sinks on the crossing points of
  the bottom layer

21
Representative Area

• Area surrounded by adjacent power pads
• Power mesh
• infinite resistive grid
• constructed by replicating the representative
  area
• Worst-case IR-drop appears near the center of the
  representative area

Power distribution networks and representative
areas for M- and Y-architectures.
22
IR-Drop in Single-Level Power Mesh

• IR-drop depends largely on the top-level mesh
• Worst-case static IR-drop on single-level
  Manhattan and Y-mesh

• NM , NY stripes in the representative area
• RM , RY edge resistance
• IM , IY total current drain in the
  representative area
• CM -0.1324, CY 0.09666

23
Verification of IR-Drop Formula

• HSpice simulations show accuracy within 1

24
Comparing IR-Drop in Single-Level Power Mesh

• Y-mesh vs. Manhattan (M-) mesh
• same wire material, thickness and total wiring
  resources
• same area ? same total current drain
• same crossing points and power pads

IR-drop improvements in single-level Y-mesh vs.
M-mesh.
C 0.02309
25
IR-Drop in Hierarchical Power Mesh

• Power network a hierarchy of metal layers
• HSpice simulations (Y- and M-meshes)
• assume equal total routing area
• same distribution of current sinks and power pad
  density
• same power distribution in M1-M3
• M4-M6
• Y-mesh 0, 120 and 240-degrees
• M-mesh 0, 90 and 0-degrees
• fix thickness and resistivity parameter for each
  layer
• exhaustively explore different configurations of
  wire pitch and width
• compare the best solutions
• Y-mesh vs. M-mesh 8.6 less worst-case IR-drop

26
Outline

• Throughput Analysis
• Wirelength Reduction
• Y Clock Tree
• IR-Drop of Y Power Distribution
• Routability
• uniform routing grid
• via tunnels and via tunnel banks
• Manufacturing Issues

27
Uniform Routing Grid

• Uniform routing grid same wiring pitch in every
  routing layer
• Y- and M-architectures natural
• X-architecture identical layer pitches ? wire
  intersection points not coincident
• Benefits
• enables use of gridded routing algorithms
• simplifies manufacturing processes
• simplifies determination of legal via locations
• improves printability in subwavelength
  lithography
• permits integral coordinates, and simplifies
  detailed routing and design rule checking

28
Via Tunnels and Via Tunnel Banks

• Via blockage effects
• vias traditionally scattered over the chip
• cause fragmentation of routing resources
• lead to serious wirability problems
• Via tunnels and Via tunnel banks
• avoid via blockage effects
• improve overall chip routability

29
Via Tunnel in the Y-Architecture

• Via tunnel detour wires around the through via
  using tracks in the middle layer
• Three layers 60-, 120- and 0-degrees from top to
  bottom
• blockage-free on top and bottom layer
• five tracks blocked in the middle layer

30
Bank of Via Tunnels in the Y-Architecture

• Bank of via tunnel align a number of via tunnels
  along the 120-degree direction
• L via tunnels, k vias in each via tunnel
• Overhead 2k 1 tracks on the middle layer

31
Outline

• Throughput Analysis
• Wirelength Reduction
• Y Clock Tree
• IR-Drop of Y Power Distribution
• Routability
• Manufacturing Issues

32
Mask Making

• Partial solution (I) Write angled lines with a
  series of small shots
• Vector Shaped Beam lithography tools such as JEOL
  JBX3030
• X-architecture 45-degree pattern produced with
  high speed
• Throughput a pair of rectangular apertures
  rotated to the desired angle
• Partial solution (II) Use optical (laser)
  lithography for applications of Y-architecture to
  upper, low-resolution metal layers
• ETEC Alta mask writing tools

33
Other Manufacturing Issues

• Other challenges
• mask inspection, exposure tools, repair,
  metrology, and pattern compensation
• The deployment of the Y-architecture will depend
  on engineering efforts across several domains,
  but we believe that there are no show-stoppers.

34
Conclusions

• Examined key issues concerning the potential use
  of Y-architecture for semiconductor ICs
• Ongoing work
• theoretical analysis and high-impact designs or
  codes to demonstrate Y-architecture advantages
• accurate estimations of wirelength improvement
  which formalizes interactions between nets
• interfaces to current library cells and new
  Y-specific library cells

35
Thank You !