Allen Cheng, Gary Tyson , Trevor Mudge

1
FITS Framework-based Instruction-set Tuning
Synthesis for Embedded Application Specific
Processors

• Allen Cheng, Gary Tyson , Trevor Mudge
• Advanced Computer Architecture Lab
• The University of Michigan
• Department of Computer Science
• Florida State University

2
Challenges Solutions

• The constraints are growing ever-tighter
• Performance
• Area 5
• Power 711
• Cost
• Time-to-market
• Improving Code Density
• Application-Specific Designs
• General-purpose Fabrication

3
Related Work

• Dual instruction sets (e.g. ARM/Thumb)
  12610
• Supports both 32-bit 16-bit instruction sets
• Dual-width instruction set (e.g. ARM/Thumb2) 3
• One ISA combines both 32-bit 16-bit instructions

16-bit Good ! Restrictive Bad !
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A Philosophy that FITS !

• Single 16-bit ISA design
• Large (unmapped) instruction set
• Map instructions for needs of each application

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A Theme that FITS !
Small but Powerful !!!
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An Architecture that FITS !

• General-purpose underlying microarchitecture
• Full range of functional capabilities
• Programmable decoder
• Maps only a subset of needed insns to the 16-bit
  format
• Why programmable decoder?
• Decouple the µ-arch enhancements from IS encoding
• Post-fabrication instruction set mapping
• Match the dense coding capabilities of ASP
• Retain fabrication advantages of a single chip

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How FITS fits into Design Frame
Architectural Design Space

Speed Efficiency
Programmability Flexibility
ASIC
ASP
GPP
DSP
GPPExt
Applicable Range
FITS
SAVE Code Size, Power, Time to Market, Cost
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Design Synthesis Heuristic

• Instruction synthesis
• Utilization-based category-partitioning
• Instruction categories
• Base Instruction Set (BIS) 5 instr
• Supplemental Instruction Set (SIS) 5 instr
• Application-Specific Instruction Set (AIS) 3-5
  instr
• Immediate synthesis
• Utilization-based dictionary-compression 4
• Immediate target
• ALU Immediates
• Memory Immediates

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BIS
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BIS SIS
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BIS SIS AIS
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Top 16 ALU Immediates
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Top 16 Memory Immediates
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Code Size Benefits
50 Saving!
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Conclusions

• Constraints are tight
• Improve code density
• General purpose microarchitecture
• Programmable decoder for post-fabrication IS
  tuning
• Results
• Small Area
• Low Cost
• Low Power
• High Performance
• Fast Time to Market

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References

• 1 ARCtangent-A5 microprocessor Technical
  Manual, ARC Cores, http//www.arccores.com.
• 2 ARM7TDMI technical Manual. ARM Ltd.,
  http//www.arm.com.
• 3 ARM Thumb-2 Core Technology, ARM Ltd.,
  http//www.arm.com/armtech/Thumb-2.
• 4 C. Lefurgy, E. Piccininni, and T. Mudge,
  Reducing Code Size with Run-time Decompression,
  in Proceedings of 6th International Symposium on
  High-Performance Computer Architecture (HPCA),
  Jan. 2000, pp. 218-227.
• 5 D. Keitel-Sculz, N. When, Embedded DRAM
  Development Technology, Physical Design, and
  Application Issues, IEEE Desisn and Test of
  Computers, vol. 18, no. 3, pp. 7-15, May/June
  2001.
• 6 K. D. Kissell, MIPS16 High-density MIPS for
  the Embedded Market, in Proceedings of Real Time
  Systems '97 (RTS97), 1997.
• 7 L. D. Paulson, Low-power chips for
  high-powered handhelds, Computer, vol. 36, no.
  1, pp. 21-23, Jan 2003.
• 8 MiBench v.1.0, http//www.eecs.umich.edu/miben
  ch.
• 9 SimpleScalar LLC, http//www.simplescalar.com.
  
• 10 ST100 Technical Manual, STMicroelectronics,
  http//www.st.com.
• 11 T. Mudge, Power A First-Class
  Architectural Design Constraint, Computer, Los
  Alamitos, vol. 34, no.4, pp. 52-58, Apr. 2001.

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QA / Suggestions
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BACKUP FOILS
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Performance Benefits
High Code Density Improved Hit Rate
Performance