Gate Sizing: FinFETs vs' 32nm Bulk MOSFETs

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Gate SizingFinFETs vs. 32nm Bulk MOSFETs

• Brian Swahn
• Soha Hassoun
• Department of Electrical and Computer Engineering
• Department of Computer Science
• Tufts University

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Outline

• FinFET device structure
• FinFET and 32nm bulk MOSFET I-V characteristics
• Gate sizing methodology
• Experimental results
• Final thoughts

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FinFET Transistor Structure

• The finFET consists of a channel, source, drain,
  and gate
• Quasi-planar device current flows parallel to
  the plane of wafer
• Fin height is a process-fixed parameter
• Device width W 2 x Hfin

D. Hisamoto, W.-C. Lee, J. Kedzierski, E.
Anderson, H. Takeuchi, K. Asano, T.-J. King, J.
Bokor, and C. Hu. A Folded-Channel MOSFET for
Deep-Sub-Tenth Micron Era. IEEE International
Electron Devices Meeting 1998, pages 10324, 1998.
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Building Wider FinFETs
Multi-fin device

• Wider finFETs are achieved by placing multiple
  fins in parallel
• Total device width Wtot 2 x Hfin x n

K. Bernstein and C. Chaung and R. Joshi and R.
Puri, Design and CAD Challenges is Sub-90nm CMOS
Technologies, International Conference on
Computer-Aided Design, 12936, 2003.
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Impact of Fin Thickness on Performance

• Thicker fins increase Ion by 1-2x and Ioff by 3
  orders of magnitude

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FinFET vs. 32nm Bulk MOSFET I-V Comparison

• FinFETs improve Ion by 2-3x, reduce Ioff by 2.5
  orders of magnitude

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FinFET Gate Sizing

• Must meet given constraints
• Traditional gate sizing has been studied
  extensively over the past several decades,
  resulting in numerous approaches
• Exact vs. heuristic
• Convex vs. linear
• Simplified delay models vs. lookup tables
• Unlike traditional gate sizing, finFET gate
  sizing is a discrete optimization problem
• Width of device based on the number of fins

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Issues in Gate Sizing

• Discrete vs. continuous
• FinFET device sizes are discrete, similar to
  library gate sizes.
• Gate vs. body biasing
• FinFETs utilize independent gating with gate
  biasing to achieve power reductions, similar in
  spirit to adaptive body biasing in traditional
  MOSFETs
• Fin width
• FinFET fin width can be adjusted to trade power
  for performance

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Delay is a Function of Temperature

• Mobility and threshold voltage are temperature
  dependent
• As T?, ?? and VT?

FinFET delay
32nm Bulk MOSFET delay
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Modeling Using Logical Effort

• Model describes gate delays from capacitive
  loading
• Delay of a gate consists of four quantities
• Logical effort (g)
• Electrical effort (h)
• Parasitic delay (p ? ? pinv)
• Process delay unit (?)
• Process (?) and parasitic inverter (pinv) delays
  are applied to all gates
• Incorporate environmental, device, and
  architectural parameters (temp, Wfin, biasing,
  etc.)
• Obtained by curve fitting process simulation data

I. Sutherland, B. Sproull, and D. Harris.
Logical Effort Designing Fast CMOS Circuits.
Morgan Kaufmann Publishers Inc., 1999.
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Delay Modeling Based on Logical Effort

• Integer restrictions are placed on gate scale
  factors (ni)
• From thermal analysis, maximum device temperature
  rise can be controlled (setting nmax)

B. Swahn and S. Hassoun. METS A Metric for
Electro-Thermal Sensitivity and Its Application
to FinFETs. International Symposium on Quality
Electronic Design, pages 1216, 2006.
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Model Calibration

• We calibrate the temperature dependent
  parameters, ? and Pinv, at different temperatures
  with different parameters
• The parameters are then used during gate sizing,
  based on a maximum expected source temperature

I. Sutherland, B. Sproull, and D. Harris.
Logical Effort Designing Fast CMOS Circuits.
Morgan Kaufmann Publishers Inc., 1999.
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Gate Sizing Problem Power Minimization

• Active Power
• Standby Power
• Total Power

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Optimization

• Problem formulated as a Mixed Integer Non-Linear
  Program (MINLP) as well as NLP-based heuristic
• We solve via the SBB package in the General
  Algebraic Modeling System (GAMS)
• Optimization objectives
• Minimize power (active, standby, or both) based
  on delay and temperature constraints

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FinFET Gate Sizing Results

• Dynamic power split evenly between switching
  power and short circuit power
• Majority of devices were minimum fin thickness
  and size
• Few devices employed independent gating
• Large delay overhead associated with independent
  gating

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32nm Bulk Gate Sizing Results

• 32nm bulk circuits are 4.5x slower than finFET
  circuits
• FinFETs reduce standby power consumption by 2-3
  orders of magnitude

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Final Thoughts

• Gate sizing results indicate finFETs improve
  performance and reduce power when compared to
  32nm bulk MOSFETs
• This work provides the first detailed comparison
  between finFETs and 32nm bulk MOSFETs at the
  device and circuit level
• Paves the way for future finFET device and
  circuit level optimizations
• This work was supported by a gift from Altera
  Corp. and a grant from the National Science
  Foundation