Counters - PowerPoint PPT Presentation

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Counters

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Counters – PowerPoint PPT presentation

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Title: Counters


1
Counters
  • Mano Kime
  • Sections 5-4, 5-5

2
Counters
  • Ripple Counter
  • Synchronous Binary Counters
  • Design with D Flip-Flops
  • Design with J-K Flip-Flops
  • Counters in VHDL

3
Counters ---
4
A 4-bit Ripple Counter
Less Significant Bit output is Clock for Next
Significant Bit! (Clock - active low)
Recall...
5
J-K Flip-Flop from a D Flip-Flop
DQ J !Q !K Q
DQ Q DQ 0 DQ !Q Q 1 DQ !Q
6
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8
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9
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10
Counters
  • Ripple Counter
  • Synchronous Binary Counters
  • Design with D Flip-Flops
  • Design with J-K Flip-Flops
  • Counters in VHDL

11
Divide-by-8 Counter
12
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
0
1
1
1
1
Q2.D
Q2.D !Q2 Q1 Q0 Q2 !Q1
Q2 !Q0
13
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q1.D
Q1.D !Q1 Q0 Q1 !Q0
14
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q0.D
Q0.D ! Q0
15
CUPL Simulation Output File
16
3-Bit Down Counter
17
3-Bit Down Counter
Q1 Q0
00
01
11
10
Q2
1
0
1
1
1
1
Q2.D
Q2.D !Q2 !Q1 !Q0 Q2 Q1
Q2 Q0
18
3-Bit Down Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q1.D
Q1.D !Q1 !Q0 Q1 Q0
19
3-Bit Down Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q0.D
Q0.D ! Q0
20
Up-Down Counter
Up-Down Counter
clock
Q0 Q1 Q2
UD
UD 0 count up UD 1 count down
21
Up-Down Counter
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1
0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0
1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1
1 1 1 1 1 0
0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1
0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1
0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0
1 1 1 0 0 0
Up-Counter
Down-Counter
22
Up-Down Counter
Q1 Q0
00
01
11
10
UD Q2
00
01
11
10
Make Karnaugh maps for Q2.D, Q1.D, and Q0.D
23
Counters
  • Ripple Counter
  • Synchronous Binary Counters
  • Design with D Flip-Flops
  • Design with J-K Flip-Flops
  • Counters in VHDL

24
Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter
25
Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter
26
Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter
27
Synchronous Binary Counters
J-K Flip Flop Design of a Binary Up Counter
28
4 - Bit Counter Logic Diagram
29
Counters
  • Ripple Counter
  • Synchronous Binary Counters
  • Design with D Flip-Flops
  • Design with J-K Flip-Flops
  • Counters in VHDL

30
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31
4-Bit Binary Counter with Reset
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