1
 Trends in high speed, low power Analog to
Digital converters 

• Laurent Dugoujon
• Data-Converters Design Mgr.

2
Outline

• Introduction/Generalities
• ADC challenges
• ST ADC products
• Power Optimisation
• Design views
• ADC Trends
• Conclusion

3
Introduction/Generalities

• DEFINITIONS

4
Analog to Digital Converter(ADC)
Ex4 bits A/D converter.
010010111
1
ADC
D0
1
D1
DIGITAL
D2
1
OUTPUT
TSA04XX
D3
Full scale amplitude
LSBFull scale/2N
62mV for 1V/4bits
16 possible output codes
5
ADC MAIN PARAMETERS

• ADC functionality parameters
• Number of output bits
• Sampling frequency noted FS
• Number of channels
• ADC performance parameters
• Static parameters DNL, INL
• Dynamic parameters SNR, SINAD, ENOB, Analog
  input bandwidth.
• Power consumption, Area, Package

6
Generalities

• ADC Market, Applications

7
ADC Market

• SourceWSTS

• ADC, DAC, SWITCHES MUX
• Regions
• US 42
• Europe 22
• Japan 18
• A/P 16
• Year 2000
• 1.8B total value
• 646Mu total volume

8
High Energy PhysicsElectronic chain
Detector
Data Processor
DAQ DCS
ADC
PA
Storage Control Analysis
Sensor
Signal formating
Events acquisition
9
Hi-volumes Hi-tech Applications
Consumer Audio
HEP Detectors requirements
Industrial Control
low Power no. channels
Nbr. bits
Consumer Video
10
HEP
Telecom
RF/Military
AP
10MHz
Astro-Physics
Sampling Frequency
10
ADC Challenge

• ACCURACY and SPEED?

11
Speed-Accuracy coupling

• Fundamental relation (Heisenberg)
• DE . DT m h/2.p
• DE (LSB/2)2 / R
• DT T/2
• Applied to A/D Converter
• R50 Ohms, 2N.LSB 1Volt, h6.626 10-34
• 2N.Fsamp lt 3.44 1015
• ex 12 bits/840Gsamples/s
• Or 18bits/10Gsamples/s

Vin
LSB/2
T/2
Time
12
Real signals world

• How many Gigabit/s on a wire ?
• Today commercial 10Gbit/s with ECL levels
• Power, EMI, Integrity loss, Package
  parasitics,.. Are the limiting factors against
  higher rates !

13
Clock accuracy problems

• Generation of Clock signal
• Clock signal is usually the fastest signal of the
  acquisition system and determines the sampling
  instants

signal
jitter
clock
14
Low-jitter Clock generation

• Clock jitter
• It characterizes the Quality of the time
  reference, often expressed in ps pk-to-pk or rms.
• Available generator technologies
• RC Logic Xtal, VCXO Sp. Plls
• Jitter 100-1000ps 10-100ps 0.5-10ps
• Cost 0.1 1 10

15
Clock Quality vs ADC specs

• Aperture time and Clock jitter for a Nbit ADC
  sampling an Analog signal of FIN frequency must
  be less than
• 1/(PI x FIN x 2(N1) )
• In order not to add degradation in the achieved
  Signal/Noise Ratio.
• Example 10 bit conversion of 10MHz input needs
  less than 16ps jitter. (good quality Xtal
  oscillator is OK)
• 12bit of same 10MHz input needs 4ps max jitter !

16
Accuracy/speed
Effect. bits
22
Heisenberg
20
18
16
1ps jitter
14
12
10
8
6
4
2
Sample rate S/s
0
10K
100K
1M
10M
100M
1G
10G
100G
17
Sampling rate trend summary

• Today best system clock jitter is 1ps
• Corresponding to 12bit resolution of 40MHz
  input signal
• Prototypes ADCs reach 0.5ps aperture time
  (8bit/1.3GHz)
• Going beyond 12bit-40MHz will require sub-ps
  jitter clock generator preferably integrated to
  the ADC chip for noise, power and cost reductions.

18
Resolution Problems

• Resolution of real conversion systems is limited
  by the  noise floor  resulting from differents
  noise sources thermal noise, transistors
  intrinsic noise,
• Input-referred noise can be expressed as
• ltvn2gt 4 kTReqFs/2
• This should be less than Quantization noise that
  is
• Q2/12, QFull scale/2N
• Then
• N lt Log2Vfs2/(6kTReqFs)1/2 1
• Given a 2Volts full scale and 1000ohms Req, it
  gives
• 19bit sampling at 100Ksps (or 16bit at 10Msps)

Req
Noiseless ADC
Rnoise Equiv.
Vin
19
Accuracy/speed
Effect. bits
22
Heisenberg
20
1Kohm thermal
18
16
1ps jitter
14
12
10
8
6
4
2
Sample rate S/s
0
10K
100K
1M
10M
100M
1G
10G
100G
20
High-speed ADCs ST products services
TSA0801 8-bit, single-Channel, 40Msps,
40mW TSA1001 10-bit, single-Channel, 25Msps,
35mW TSA1002 10-bit, single-Channel, 50Msps,
50mW TSA1201 12-bit, single-Channel, 50Msps,
130mW TSA1203 12-bit, dual-Channel, 40Msps,
230mW TSA1204 12-bit, dual-Channel, 20Msps,
120mW TSA1005 10-bits, dual Channel, 40 Msps,
200mW
2.5V supply voltage
TQFP48
Evaluation boards, Applications notes, support,
IP integration, consulting
21
ST ADCs Accuracy/speed
Effect. bits
22
Heisenberg
20
1Kohm thermal
18
16
1ps jitter
14
products
12
10
8
6
prototypes
4
2
Sample rate S/s
0
10K
100K
1M
10M
100M
1G
10G
100G
22
Power optimisationMeritFig.2ENOB x Fs / Power
( x 10-11 )
TSA1002 9.7b, 50Msps 50mW MF8.3
ADCs Vsupply2.5V
TSA1001 9.7b, 25Msps 35mW MF5.9
TSA1201 10.5b, 50Msps 130mW MF5.6
TSA1203 (dual) 10.5b, 40Msps 230mW MF5
TSA0801 7.9b, 40Msps 40mW MF2.4
Closestcompetitor MF3.2
Closestcompetitor MF4.2
Closestcompetitor MF4.7
Closestcompetitor MF2
Competitors Vsupply 5V or 3.3V
Closest competitor MF1.2
23
Designarchitectures
24
Very High Speed ADC (8bits/2Gsps)

• Interleaved SAR ADCs

0.18mm CMOS
8
MUX
SA ADC 1
121
8
8
SA ADC 12
V
8
IN
SA ADC 13
MUX
121
8
8
SA ADC 24
24 // unitary SAR ADC
Die 4mm2, IP 0.45mm2
25
Pipelined ADCs
1 pipeline stage
Vi-1
Vi
S/H
x2
2bit
2bit
Digital correction
Output bits
26
Folded-cascode Amplifier
2.5V / 0.25mm CMOS
VtpVtn0.7V
G90dB THD-86dB BW3dB100MHz
27
CERN Alice-TPC ALTRO chip
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CERN ALTRO chip Layout and Package
7.7 mm
24mm
TQFP 176
3.8 mm
8.3 mm
Pedestal Memory 1K x 10
Data Memory 1K x 40
Processing Logic
29
CERN ALTRO ADC results
30
ADC Power Consumption
Optimised ADC power in ALTRO
ADC Operating Point
Effective Number of Bits
9.7
Power Consumption per Channel
30 mW
12 mW
90 kW
20 kW
Measured Analogue Power Consumption 80
mA (st.dev 1.12 mA) 12.5 mW / channel
MPW values Engineering Run values
31
CERN ALTRO spectrum analysis
32
ALTRO chip Digital Processor Performance
INPUT SIGNAL
AFTER 1st BASELINE CORRECTION
AFTER TAIL CANCELLATION
AFTER 2nd BASELINE CORRECTION
33
ADC Trends

• Resolution-Speed
• Paralelism to exploit technology intrinsic speed
  of successive generations technology (X2 every
  2years)
• Intensification of integrated Digital
  Post-processing
• Number of channels
• Lower core sizes and power will allow higher
  integration
• Associated Functions
• Internal Clock re-generation will appear,
  Built-In-Self-Test,
• Power
• New low-voltage cells/architectures for 1V
  technology on the way
• Packages
• Parasitics and size reduction associated to
  better dissipation

34
Conclusions

• ADCs are used in many applications
• HEP is not so specific in terms of need
• Application Environment can degrades ADC perf.
• High Merit-figure ADC design needs large efforts
• Multi-ADCs integration is a powerfull path
• Digital integration is the same natural path
• We will use Moores law to buy resolution.speed