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Arithmetic Circuits

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Half adder: without carry in. Two ... Gi PiCi. 1. 1. 1. 0. 1. 0. 0. 0. Cout. 1. 0. 0. 1. 0. 1. 1. 0. S. 1. 1. 1. 1. 0. 0. 0. 0. Cin. 1. 1. 0. 0. 1. 1. 0 ... – PowerPoint PPT presentation

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Title: Arithmetic Circuits


1
Arithmetic Circuits
2
Outline
  • Adders
  • Multipliers
  • ALU Design

3
Adders
  • Half adder without carry in
  • Two inputs
  • Two outputs sum and carry out
  • Full adder with carry in
  • Three inputs include carry in
  • Two outputs sum and carry out

4
Half Adder
  • S A?B
  • Cout AB

A B S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
5
Full Adder
  • S A?B?Cin
  • Cout ABBCin ACin

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
6
Full Adder
7
4-bit Parallel Adder
8
4-Bit Adder-Subtractor
9
4-Bit Adder-Subtractor
10
Carry Look-Ahead Logic
11
Carry Look-Ahead Logic
  • Pi Ai ? Bi (carry Propagate)
  • Gi AiBi (carry generate)
  • Si Ai ? Bi ? Ci Pi ? Ci
  • Ci1 AiBi BiCi AiCi
  • Gi (Ai Bi)Ci
  • Gi (Ai ? Bi)Ci
  • Gi PiCi

Cin A B Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
12
Carry Look-Ahead Logic
  • C1 G0 P0C0
  • C2 G1 P1C1 G1 P1 (G0 P0C0) G1 P1G0
    P1P0C0
  • C3 G2 P2C2 G2 P2G1 P2P1G0 P2P1P0C0
  • C4 G3 P3C3 G3 P3G2 P3P2G1 P3P2P1G0
    P3P2P1P0C0
  • S0 A0 ? B0 ? C0
  • S1 A1 ? B1 ? C1
  • S2 A2 ? B2 ? C2
  • S3 A3 ? B3 ? C3

13
Carry Look-Ahead Logic
14
BCD Addition
  • A BCD adder is a circuit that adds two BCD digits
    in parallel and produces a sum digit also in BCD.
    Consider the sum in BCD and binary
    representations in 5 bits

15
Decimal Cout B8 B4 B2 B1 Cout S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1
2 0 0 0 1 0 0 0 0 1 0
3 0 0 0 1 1 0 0 0 1 1
4 0 0 1 0 0 0 0 1 0 0
5 0 0 1 0 1 0 0 1 0 1
6 0 0 1 1 0 0 0 1 1 0
7 0 0 1 1 1 0 0 1 1 1
8 0 0 0 0 0 0 1 0 0 0
9 0 1 0 0 1 0 1 0 0 1
10 0 1 0 1 0 1 0 0 0 0
11 0 1 0 1 1 1 0 0 0 1
12 0 1 1 0 0 1 0 0 1 0
13 0 1 1 0 1 1 0 0 1 1
14 0 1 1 1 0 1 0 1 0 0
15 0 1 1 1 1 1 0 1 0 1
16 1 0 0 0 0 1 0 1 1 0
17 1 0 0 0 1 1 0 1 1 1
18 1 0 0 1 0 1 1 0 0 0
19 1 0 0 1 1 1 1 0 0 1
16
BCD Addition
17
BCD Addition
18
Magnitude Comparator
  • 1-bit comparator
  • F AiBi Ai' Bi' (Ai ? Bi)'
  • Flt Ai'Bi
  • Fgt AiBi'

A B F Flt Fgt
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0
19
2-bit Comparator
  • Suppose N1 A1A0, N0 B1B0
  • Case 1 N1 N0 -- A1 B1 and A0 B0
  • F (A1 ? B1)' (A0 ? B0)'
  • Case 2 N1 lt N0 -- A1lt B1 or A1 B1 and A0 lt B0
  • Flt A1'B1 (A1 ? B1)' A0'B0
  • Case 3 N1 lt N0 -- A1gt B1 or A1 B1 and A0 gt B0
  • Fgt A1B1' (A1 ? B1)' A0B0'

20
Multiplier
  • Partial product accumulation
  • 1001 (9)
  • 1101 (13)
  • ----
  • 1001
  • 0000
  • 1001
  • 1001
  • -------
  • 1110101 (117)
  • 64321641 117

21
2-Bit Multiplier
  • A1 A0
  • B1 B0
  • -------
  • A1B0 A0B0
  • A1B1 A0B1
  • ---------------
  • S3 S2 S1 S0

22
4-Bit Multiplier
  • A3 A2 A1 A0
  • B3 B2 B1 B0
  • ---------
  • A3B0 A2B0 A1B0 A0B0
  • A3B1 A2B1 A1B1 A0B1
  • A3B2 A2B2 A1B2 A0B2
  • A3B3 A2B3 A1B3 A0B3
  • -----------------------------------
  • S7 S6 S5 S4 S3 S2 S1 S0

23
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24
Arithmetic Logic Unit (ALU) Design
25
ALU
S1 S0 Cin Yi F
0 0 0 0 F A
0 0 1 0 F A 1
0 1 0 B F A B
0 1 1 B F A B 1
1 0 0 B' F A B'
1 0 1 B' F A B' 1
1 1 0 1 F A -- 1
1 1 1 1 F A
S1 S0 Yi
0 0 0
0 1 B
1 0 B'
1 1 1
Xi Ai
Yi s0Bi s1Bi'
Cin Cin
26
Example
  • Design one bit slice for an ALU unit using a full
    adder block to perform the following

M S1 S0 Function Name F Xi Yi Cin
0 0 0 Complement A' Ai' 0 0
0 0 1 AND A AND B Ai AND Bi 0 0
0 1 0 Identity A Ai 0 0
0 1 1 OR A OR B Ai OR Bi 0 0
1 0 0 Decrement A - 1 Ai 1 0
1 0 1 Add A B Ai Bi 0
1 1 0 Subtract A B' Ai Bi' 1
1 1 1 Increment A 1 Ai 1 1
27
Example
Determine Yi
M S1 S0 Yi
1 0 0 1
1 0 1 Bi
1 1 0 Bi'
1 1 1 0
Yi MS1'Bi MS0'Bi'
Determine Xi
M S1 S0 Xi
0 0 0 Ai'
0 0 1 Ai Bi
0 1 0 Ai
0 1 1 Ai Bi
1 X X Ai
Xi M'S1'S0'Ai' M'S1S0Bi S0AiBi S1Ai
MAi Cin MS1
28
(No Transcript)
29
Example
  • Design one bit slice for an ALU unit using a full
    adder block to perform the following

M S1 S0 Function Name F Xi Yi Cin
0 0 0 Add A B Ai Bi 0
0 0 1 Subtract A - B Ai Bi' 1
0 1 0 Increment A 1 Ai 0 1
0 1 1 Decrement A - 1 Ai 1 0
1 0 0 AND A AND B Ai AND Bi 0 0
1 0 1 OR A OR B Ai OR Bi 0 0
1 1 0 Complement A' Ai' 0 0
1 1 1 XOR A ? B Ai ?Bi 0 0
30
Example
Determine Yi
M S1 S0 Yi
0 0 0 Bi
0 0 1 Bi'
0 1 0 0
0 1 1 1
Yi M'S1S0 M'S1S0Bi M'S0'Bi'
Determine Xi
M S1 S0 Xi
1 0 0 Ai Bi
1 0 1 Ai Bi
1 1 0 Ai'
1 1 1 Ai ?Bi
0 X X Ai
Xi MS1S0'Ai' MS0Ai'Bi MS1'AiBi MS0AiBi'
M'Ai Cin M' (S1 ?S0)
31
Exercises
  • p. 325 4.32, 4.33, 4.34, 4.36, 4.37, 4.39, 4.40,
    4.43, 4.44
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