Pointer Analysis for Instruction Level Parallelism

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Pointer Analysis for Instruction Level
Parallelism
Rami Beidas Jeff DaSilva
ECE1718 April 28, 2004
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Motivation
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Motivation

• Software developers utilize powerful pointer
  constructs to realize complex data structure.
• Optimizing compilers are typically conservative
  with memory references that use pointers.
• Efficient pointer alias analysis algorithms and
  tools do exist.
• SPAN

?Can a real pointer alias analysis tool improve
performance?
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Project Objectives

• Determine the maximum available instruction level
  parallelism when limited by a real pointer
  analysis tool.
• Design a framework for evaluating the
  effectiveness of any pointer analysis tool.

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Project Flow Graph
Simple Scalar Simulator
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Annotating Static Memory References
int x, y int p_xx int p_yx p_x
if() p_y p_x p_y p_y
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Pointer AnalysisLoad-Store Dependence Matrix
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Pointer AnalysisDynamic Profiling Matrix
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Pointer AnalysisSPAN
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int x, y
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30,31
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ASM Annotation
Simple Scalar Simulator

• Alias-analysis results identify bounded memory
  access regions
• The need to pass alias-analysis results to
  SimpleScalar Simulation engine

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ASM Annotation
STR_BEGIN()
ASM OP (ANNOT1) ()
a b
STR_END
ASM OP (ANNOT2)

• The use of SimpleScalar annotation interface to
  pass alias analysis results

16-ANNOT
16-op
8-rs
8-rt
16-imm
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Simple Scalar Simulator

• Similar approach to HW1
• Schedule instructions, including memory accesses,
  ASAP
• Each memory access needs to be schedules when
  parameters are available AND All CONFLICTING
  MEMORY ACCESSES ARE COMPLETED

Simple Scalar Simulator
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Simple Scalar Simulator
Mem Access 1

• Annotation instructions identify current memory
  access ID
• Check all conflicting memory accesses
• Schedule after the last conflicting access

Mem Access 2
Mem Access 3
. . .
Mem Access N
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Results
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Results
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Results
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Results
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Conclusion

• Argued the benefits of using alias analysis
  results in enhancing ILP
• Proposed a well-defined methodology and framework
  to measure the effect of using static pointer
  analysis results on ILP
• Presented the potential benefits of
  memory-related static-analysis on ILP of a number
  of testbenches

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Future Work

• More experimental results on pointer-intensive
  applications
• A more realistic memory system
• A more realistic micro-architecture model (e.g.
  sim-outorder)