Leakage-and Crosstalk-Aware Bus Encoding for Total Power Reduction

1
Leakage-and Crosstalk-Aware Bus Encoding
forTotal Power Reduction

• Harmander S. Deogun
• Rajeev R. Rao Dennis Sylvester David Blaauw
  DAC04

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Agenda

• Introduction
• Encoding
• Experimental Results
• Conclusions

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Agenda

• Introduction
• Encoding
• Experimental Results
• Conclusions

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Introduction

• Total power
• Leakage power
• Dynamic power
• Dual Vth
• High Vth leakage?, dynamic?, delay?

Staggered Threshold Voltage
Minimize Bit Transition
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Staggered Threshold Voltage
Off-state Active
Input 0
Input 1
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Tradeoff Between Dynamic Energy and Delay
Penalty
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Agenda

• Introduction
• Encoding
• Experimental Results
• Conclusions

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Encoding

• Leakage-aware
• Skew the input data bits of the bus to either the
  0 or 1 state.
• Crosstalk-aware
• Eliminate the worst-case transition between a
  pair of adjacent wires.
• (01?10 or 10 ?01)

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Encoding Features

• Eliminate crosstalk between adjacent bus lines
• Minimize leakage by skewing the probability of
  the bits
• Minimize overhead due to the encoding and
  decoding logic

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Encoding

• Encode 3-bits of input as 4-bits codewords.
• Split the 32-bit bus into sets of 3-bits each and
  then encode each set individually.
• A shield (dedicated ground or Vdd wire) separates
  each set.

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Lemma

• The ideal codeword in a codebook that satisfies
  these features does not contain two adjacent bits
  that are the same.

b1b1b3b4
b1b2b3b4
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4-bit Codewords
0101
HD 1 1101 0001 0111 0100
HD 2 1001 1111 1100 0011 0000 0110
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Algorithm
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Agenda

• Introduction
• Encoding
• Experimental Results
• Conclusions

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Experimental Results(1/3)
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Experimental Results(2/3)
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Experimental Results(3/3)
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Agenda

• Introduction
• Encoding
• Experimental Results
• Conclusions

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Conclusions

• Average 26 total power savings, with a best case
  savings of 44.