VFE tests - varying hold, DAC, and enable (Run 1080065286)

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VFE tests -varying hold, DAC, and enable(Run
1080065286)

• Catherine Fry
• 25th March 2004

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2

• Look at channel 3 of chip 8 (connected and has
  TCALIB).
• For each enable (0, 1, 2, 3, 4, 5) plot mean ADC
  against hold for DAC 0, 500, 1000, 1500, 2000.
• Look to see which enable gives different response
  for different DAC values.

2
3
Enable 0
3
4
Enable 1
4
5
Enable 2
5
6
Enable 3
6
7
Enable 4
7
8
Enable 5
8
9

• Summary of results from chip 8 channel 3
• Do not see expected change in response from the
  different DAC values as change enable.
• No consistent time for when ADC value starts to
  rise.
• Enables 1 and 4 have similar strange shape and
  high peak value of ADC (17000 and 24000).
• Enables 2, 3 and 5 show beginning of a second
  peak.
• Peak ADC value ranges from 1800 to 24000 counts.
• Enables 0, 1 4 take about 200ns to reach peak.
• Enables 2, 3 5 take about 300ns to reach peak.
• Get similar variety of plots for the other
  channels of chips 8 9.
• For chip 2 (without TCALIB), get the same shape
  response for all channels and all enables
  (similar to enable 0 of chip 8 channel 3 - slide
  3). Except channels 4 and 9 which show no
  response.

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• Pattern in channels of chips 8 and 9?

Chan/Enable 0 1 2 3 4
0 A A A A A
1 A A A A A
2 A A A A A
3 B A B B A
4 B A B B A
5 B A B B A
6 B B A B B
7 B B A B B
8 B B A B B
9 A A A A A
10 A A A A A
11 A A A A A
12 B A B B A
13 B A B B A
14 B A B B A
15 B B A B B
16 B B A B B
17 B B A B B
18 B B A B B
19 B B A B B
From run 1079372409 DAC 1000 A ADC begins
to rise from hold0ns B ADC begins to rise at
holdgt200ns
In run 1080065286 (vary DAC) the As which are
starred are now Bs (only checked chip 8)
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