Title: Design of a 4-Bit ALU
1Design of a 4-Bit ALU
EE166 Project Presentation
- Presented by
- Preeti Chauhan, Aung Moe, Harsirat Mangat
- Advisor Professor David Parent
- 12/06/2004
2Agenda
- Abstract
- Introduction Basic ALU Blocks
- -- Logic Unit
- -- Arithmetic Unit
- -- 2x1 Multiplexer
- -- D Flip-Flop
- 4-Bit ALU
- -- Schematic
- -- Size Calculations
- -- Layout
- -- Verification
- -- Simulation
- Conclusions
3Abstract
- We designed a 4 Bit ALU that operated at 200 MHz
and use 650mW of Power and occupied an area of
649 x 240 mm2
4Introduction
4-Bit ALU
Reference Digital Logic Circuit Analysis
Design by Nelson, Nagle, Irwin, and Carroll
5Logic Unit
Truth Table
Schematic
S1 S0 A B F
0 0 0 0 0 AND
0 0 0 1 0 AND
0 0 1 0 0 AND
0 0 1 1 1 AND
0 1 0 0 0 OR
0 1 0 1 1 OR
0 1 1 0 1 OR
0 1 1 1 1 OR
1 0 0 0 1 NOT
1 0 0 1 1 NOT
1 0 1 0 0 NOT
1 0 1 1 0 NOT
1 1 0 0 0 XOR
1 1 0 1 1 XOR
1 1 1 0 1 XOR
1 1 1 1 0 XOR
F S1ABS0ABS0ABS1S0A
Logic verification
6Logic Unit
LVS
7Logic Unit
Delay
82X1 Multiplexer
9D Flip-Flop
10Full Adder
Cout ABACBC Y A xor B xor C ABC (ABC)
Cout
Wp 6 um Wn4.05um Worst Case Delay 0.627ns
11Full Adder Wave_Form
Delay 677n 50n 627ns
12Y-Gen Schematic
Wp 5.55um Wn 3.45um Delay 0.86 ns
13Y-Gen and AU Logic Verification
Y S1S0B S0BS0 S1 S0 (S1B)
Cin S1 S0
14AU (Arithmetic Unit)
Cell Width 30 um Cell Length 125 um Delay
0.6270.860.4 1.887ns
Xor
15Longest Path Calculations
No of Logic Levels XOR 3 AND
2 INV 1 NAND 1 DFF
4
8
4
6
5
7
3
2
1
Delay 5ns/19 0.2ns
16Longest Path Calculations
Note All widths are in microns and capacitances
in fF
174 Bit_ALU Schematic
184 Bit_ALU Test_Bench
194 Bit ALU Wave_Form
20Layout and LVS
21Conclusions
- We are able to design a 4 Bit ALU which run at
200mHz with 600mW of power - Should work in the same account and consult with
group member to get a good layouts - More than 100 hrs of work
22Acknowledgements
- Professor David Parent
- Thanks to Cadence Design Systems for the VLSI lab
- Thanks to Synopsys for Software donation
- Thanks to my wife/husband for putting up with me.