Background Delphi Emulator

1
Background - Delphi Emulator

• Objective Design a Product Emulator using as
  much AEPT technology as possible.
• Emulator An existing product design converted
  to use and demonstrate new technology.
• Team Members
• Jiming Zhou, Delphi
• John D. Myers, Delphi
• Bill Reynolds, Delphi
• Rodney Henderson, Delphi

2
Choosing A Design To Use For An Emulator

• Past experience designing consortium test
  vehicles had taught us
• CAD tools and CAD experience with embedded
  resistors would be biggest problems.
• Delphi had 30 years experience designing MCMs.
• Pressure Sensors, Ignition Modules, Engine
  Controls
• CAD tools, Libraries and designers available.
• Using Mentor MCM Station with custom additions
• No FR-4 experience or CAD available in house
• CAD output is artwork not process definition
• Therefore Attempt to use Mentors MCM tool to
  design AEPT emulator.
• Choose a hybrid ceramic design to convert to FR-4
  with embedded passive components.

3
Choosing The Technology For The Emulator

• Resistors
• Our product requires 3 decades of resistor
  material in ohms/Sq. to cover gt85 of total
  parts.
• DuPont was only material tested with 3 decades
  available when design was started.
• Capacitors
• 3M material was only material mature enough to be
  used when design was started.

4
Actual Design Process

• No Change to CAD tool other than plug in new
  design rules
• Hybrid design rules are very different from FR-4
• Hybrids have coarse features (8/8) but very small
  capture pads (6-8 mils)
• Hybrid vias can be blind and buried, between any
  layer
• Hybrid filled vias are large (6-10 mils) but
  capture pads are smaller than vias.
• Converting blind and buried vias to through holes
  caused a major tear up of the design.
• Resistors were no problem due to good tools.
• Capacitors were difficult due to no tools.
• Delete Cap from design, hand draw trace with area
  to desired capacitance on capacitor layer.

5
Delphi Emulator Engine Control Module

• 6 Flip Chips, bump pitch as low as 8 mil on a
  stagger
• 4 Large FET bare die chip and wire devices
• 15 Small FET bare die chip and wire devices
• On Engine environment -40 to 125 degrees C
• Sealed case
• Wire bonded I/O connector to board
• Components on one side
• Heat sinking through board to aluminum case

Note Photo of original ceramic technology
6
Board Design Guidelines

• Microvias Layers 1-2
• Through hole connecting all of the other layers
• Line/Space 3/3 mils in micro fan out Layer 1,8
  else 5/5
• Min. micro via pad 14 mils
• Min. laser via 5 mils
• Min. capture pad 15 mils
• All through holes 10 mils
• Min. pad over hole 5 mils
• Min. antipad 30 mils
• Board Thickness 48 mils
• Surface finish ENiG

7
Enlargement of Microprocessor Fan Out

• Flip Chip 8mil staggered pitch
• Solder mask registration
• /- 1.5 mil
• Microvias Layers 1-2
• Fan out using 3/3 mil
• lines/spaces

8
Delphi Emulator Embedded Resistors

• 213 total Rs buried, 8 extra Rs to get values
  gt12 sq.
• Total 217 resistors
• 94 of resistors buried (205/217)
• 4 sense resistors not buried, values lt .01 Ohm
• 8 high value resistors not buried, values gt 300K
• .062 watt resistors
• 3 Resistor prints 50, 1K, 10K Ohm/Square

Purple 10k Ohm Green 1k Ohm Grey 50 Ohm
9
Delphi Emulator Embedded Resistors (continued)

• More than 10 different R shapes for .25 to 12
  squares
• 4 possible orientations / shape
• 40 mil test pads
• At least 50 mils between pads

10
Photo Of Actual PWB Resistor Layer
11
The Board Stack Up
Signal 3

• Board size 3.25 x 2.75 inch

12
Cross Section of Actual Board
Copper termination
Ceramic resistor
Encapsulation
13
Embedded Capacitors
14
Embedded Capacitors (continued)

• Total 197 capacitors
• 25 embedded, rate 25/19712.7
• 13 decoupling caps including 9 Vccl and 4 Vccd
  and Vcca. 12 filter caps.
• Theoretically 77 max embedded, rate 77/19739
• Quit after adding 12 discrete Capacitors due to
  time constraints
• Lack of CAD tools and tedious nature of manually
  changing schematic, BOM and documentation limits
  process.

15
Photo of First Article PWB, Front Side

• Final board dimensions of 2.75 x 3.25 are the
  same as original

16
Photo of First Article PWB, Back Side

• Light colored areas are coating covering embedded
  resistors to provide stress relief and reflect
  trimming laser beam.
• No components on back side