Physics%20

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Physics AstronomyHEP Electronics
TIM Requirements
ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004
John LaneMartin Postranecky, Matt Warren
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TIM Requirements

• See SCT/Pixel TIM Requirements document
• http//www.hep.ucl.ac.uk/jbl/SCT/TIM_requirements
  .html
• Interface to ROD
• Interface to BOC
• Interface to TTC
• Interface to CTP
• Interface to local trigger
• Interface to local processor
• Transmission of clock and control
• Requirement description
• Implementation
• All shown are implemented and tested

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TIM Requirements

• Interface to ROD
• Output to ROD commands and event IDs
• Implemented as crate backplane signals
• Front-end resets different from TTC resets
• Implemented as ECR and BCR
• Busy from ROD receive and monitor
• Implemented as crate backplane signals
• Interface to BOC
• Clock distribution to ROD via BOC
• Implemented as crate backplane signals

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TIM Requirements

• Interface to TTC
• Input from TTC TIM is a TTC destination
• Received by TTCrx mezzanine card
• Latency of TTC commands TIM L1A latency lt 50ns
• L1A signal clocked once on TIM
• Interface to CTP
• Busy to CTP masked OR and monitoring
• Use standard Busy module
• Busy from crate masked OR and monitoring
• TIM Busy registers

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TIM Requirements

• Interface to local trigger
• Command deadtime introduce standalone (Front-end
  protocol)
• Implemented as TIM internal busy
• Trigger latency programmable for CAL and
  external triggers
• TIM pipeline delay register
• Trigger phase timing synchronize with measurable
  phase shift
• A prompt synchronized trigger is output on front
  panel

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TIM Requirements

• Interface to local processor
• VME interface read and write access
• Implemented in firmware and external buffers
• Configuration and monitoring set and read
  registers
• TIM control and status registers
• Command execution including preloaded sequences
• TIM command register and Sequencer

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TIM Requirements

• Transmission of clock and control
• Clock source TTC system, external and internal
• Selected by TIM enable registers
• Clock stability and jitter relative to LHC phase
• Use TTCrx clock and phase-locked loop
• Clock phase delay at Front-end and ROD setup and
  hold
• TIM delay register and setup switch
• Commands required by Front-end
• Implemented in firmware
• Origin of commands TTC and standalone
• Implemented in firmware
• Latency of fast commands synchronized to bunch
• Implemented in TTCrx
• Queuing of event ID serial streams
• FIFOs buffer up to 64 events