MPIS and SPIM

1
MPIS and SPIM

• Instruction set architecture
• Registers
• Instruction format
• Memory layout
• Addressing mode
• Input/output
• Exception

2
The Instruction Set
software
instruction set
hardware
3
Instruction set What must be specified?

• Instruction format
• How is it encoded/decode
• Location operands and results
• How are memory operands located?
• How many explicit operands?
• Data type and size
• Operations
• What are supported?
• Successor instruction
• What instruction is executed next?

4
MIPS Architecture Registers and Memory
r0
r1

• Simplified instruction set
• easier to study
• Most new machines are RISC
• Programmable storage
• 31 x 32-bit GPRs (r0 0)
• special purpose - HI, LO, PC
• 32 x 32-bit FP regs
• 232 x bytes of memory
• Memory is byte addressable
• Words are 32 bits 4 bytes
• Words start at multiple of 4 address

r31
PC
lo
hi

f0
f1



f31
000000
00...0100
001000
111000
32 bits
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MIPS architecture
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MIPS Addressing Modes

• Addressing modes specify where the data used by
  an instruction is located.
• mode example action
• register direct add s1, s2, s3 s1
  s2 s3
• immediate addi s1, s2, 200 s1 s2
  200
• baseindex lw s1, 200(s2) s1
  mem200 s2
• PC-relative beq s1, s2, 200 if (s1
  s2)
• PC PC42004
• Pseudo-direct j 4000 PC (PC3128,
  40004)
• Often, the type of addressing mode depends on the
  type of operation being performed (e.g., branches
  all use PC relative)

7
Generic Examples of Instruction Format Widths

Variable Fixed Hybrid

What are the advantages and disadvantages of each
type of format?
8
MIPS Addressing Modes/Instruction Formats

• All MIPS instructions are 32 bits wide - fixed
  length

add s1, s2, s3
Register (direct)
op
rs
rt
rd
register
Immediate
addi s1, s2, 200
immed
op
rs
rt
Baseindex
immed
op
rs
rt
Memory
register

lw s1, 200(s2)
PC-relative
immed
op
rs
rt
Memory
PC

beq s1, s2, 200
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MIPS Instruction Fields R-Type and I-type

• Register type (R-type) and immediate type
  (I-type) instructions have the following formats

R-type
I-type
immed
rt
rs
op
field meaning op Basic operation of the
instruction (opcode) rs First register source
operand rt Second register source
operand rd Register destination operand (gets
result) shamt Shift amount funct Function field
- selects the variant of the operation in the
op field (function code) immed Immediate value
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MIPS registers
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MIPS architecture memory

• Byte addressable memory unit
• 4 billion bytes
• 0x00000000 to 0xFFFFFFFF
• Address Modes
• Register
• Immediate
• Baseindex
• PC-relative

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MIPS architecture memory

• Memory is organized into segments, each with its
  own purpose

0x00000000
kernel code
reserved for OS
0x00400000
text segment
0x10000000
data segment
free space, grows and shrinks as stack/data
segments change
memory addresses
(heap)
stack segment
0x80000000
reserved for the Operating System (OS)
kernel code and data
0xFFFFFFFF
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MIPS architecture memory

• Text segment
• Users executable program code
• Data Segment
• contains programs static data
• Stack Segment
• contains system stack
• System heap

14
SPIM simulator

• A freely-distributable program that simulates the
  operation of the MIPS R2000/R3000 architecture
• Unix
• X-window
• MS Windows
• Macintosh OS X

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SPIM simulator

• Machine Instructions
• Assembly Instructions
• addi 2, 6, 742
• Pseudoinstructions (software instructions)
• la a0, aLable
• System calls ( system procedures )
• Syscall
• Assembly directives
• .text, .data
• Sample program hello.a, page 26 waldron

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SPIM simulator
register values
command buttons
text segment (user code)
data and stack segments
messages