Programming Models and HWSW Interfaces Abstraction for MultiProcessor SoC

1
Programming Models and HW-SW Interfaces
Abstraction for Multi-Processor SoC

• Ahmed A. Jerraya
• TIMA Laboratory
• 46 Avenue Felix Viallet
• 38031 Grenoble Cedex France
• Tel [phone]
• Fax [phone]
• Email Ahmed.Jerraya_at_imag.fr

43rd DAC San Francisco, USA July 2006
2
From ASIC to MPSoC DesignFrom Wires to Abstract
HW/SW Interfaces

• System Level
• Abstract HW IP
• Abstract SW IP
• Abstract HW/SW Interfaces

• Classical design
• HW modules only
• wire interconnect

The programming model hides HW-SW interfaces
RTL
CPU Sub System
3
System Design Issues

• Key trend MPSoC, HW-SW Architectures
• Heterogeneous CPUs multiple SW stacks
• Key challenges
• Concurrent HW SW design to reach time-to-market
• Higher than RTL design to master complexity
• Flexible architecture to reduce NRE
• Key enabler technology HW/SW interfaces
  abstraction
• Programming models at different abstraction
  levels
• Key success factor Efficient HW-SW interfaces
  implementation
• Custom HW dependent SW
• Custom CPU subsystems
• Breakthrough New approaches to HW-SW Codesign
• CPU-HDS codesign

4
Outline

• 1.- Programming Models the Bridge between
  Hardware and Software
• 2.- Application-Specific Programming Models to
  Handle MPSoC
• 3.- Programming Models at Different Abstraction
  Levels
• 4.- Next Generation Design Flow Based on
  Programming Models
• 5.- Summary

5
The Key SoC Design Issue HW/SW Gap

• Different Concepts to Abstract Interfaces
• HW communicates through wires
• SW communicates through APIs
• SW model hides a CPU
• HW-SW interfaces includes HW, SW and CPU

SW Component foo Read (x)
HW Component Par xlt 0010
WIRES
API
Rest of the system
Rest of the system
6
Programming Model The Classical Solution to
Abstract HW-SW Interfaces

• Abstract HW model for SW development
• Programming language with implicit primitives
  (e.g. module hierarchy threads in system)
• API Application Programming Interface (e.g. MPI)
• Execution model (e.g. MPICH)
• Implementation includes HW architecture and HW
  dependent SW
• The classical programming models are used by SW
  community to liberate the SW designer from
  knowing HW details.
• The programming model concept is needed for MPSoC
  to also allow concurrent HW SW design.

SW modules
...
SW 2
SW 1
SW n
API
SW modules
SW modules
API
API
Execution Environment
HW dependent SW (HDS)
HW architecture
Simulation
Implementation
7
SW Reuse Based on Programming Model (API)
SW designed
MPEG4 (small)
MPEG4 (small)
HAL API
API
CPUx
HDSx
Comm. network
IP

• Executing same SW on different architectures
  using different CPUs
• HDS Hardware dependent Software to hide the
  architecture

8
Key Enabler Technology HW-SW Interfaces
Abstraction

• Application SW Designer A set of system calls
  used to hide the underlying execution platform.
  Also Called Programming Model
• HW designer A set of registers, control signals
  and more sophisticated adaptors to link CPU to HW
  subsystems.
• System SW designer Low level SW implementation
  of the programming Model for a given HW
  architecture.
• CPU is the ultimate HW-SW Interface
• Sequential scheme assuming HW is ready to start
  low level SW design
• System-level design requirements
• Abstracts both HW and SW in addition to CPU
• HW-SW interfaces tradeoff

Sequential SW program Call HW (x, y, z)
API
CPU specific SW
CPU (local Architecture)
x y z HW
function wait start

9
Programming Models for SoC

• Programming Model is used for software reuse
• Easy porting of application SW means easy reuse
  of application SW over different HW
  architectures that support the same APIs.
• Programming model enables concurrent SW and HW
  design
• After fixing a set of APIs,
• we can perform SW and HW design concurrently.
• Application-specific programming model design is
  needed.
• General APIs ? good portability, but heavy HDS
  implementation ? system resource/performance
  overhead
• HDS needs to be tailored to the given application
  SW,and HW architecture.
• Even when a standard API set is used, HDS can be
  tailored to implement only the APIs that are used
  by application SW.
• Intensive research area TTL (P. van der Wolf),
  JSoC (P. Paulin), MPI subset (L. Benini)

10
Outline

• 1.- Programming Models the Bridge between
  Hardware and Software
• 2.- Application-Specific Programming Models to
  Handle MPSoC
• 3.- Programming Models at Different Abstraction
  Levels
• 4.- Next Generation Design Flow Based on
  Programming Models
• 5.- Summary

11
MPSoC Architecture Trends

• Homogeneous architecture
• Multiple Instances of the same CPU
• 1 SW stack
• Standard programming model

12
Generic SoC Platform vs.Application-Specific
MPSoC
Example The GSM History/Roadmap

• 1986 Rack in a van
• 1990 PCB
• 1995 Chip set in a hand-set
• 2002 SoC
• 2006 SW component on a generic platform,
• e.g. Nomadic (ST)

Same roadmap for game computers, MP3, STB, NP, DVD
13
Application Specific MPSoC Solution for HD MPEG2
Encoding

• Example MPEG2 encoding
• 2000x1000 frame
• Full motion search 128x128 search window
• 32 TIPS (TERA instruction per second)
• All software 32 000 RISC CPU, 1Ghz
• SoC Solution 4 embedded specific CPU 200 Mhz

VASA This 60M transistor, 0.13 micronMPEG2 codec
delivers single-chip HDTVcoding thanks to 4
Xtensa cores.
14
Application-Specific Programming Model

• Automatic HW-SW interfaces design tools are
  needed to reduce MPSoC design efforts.
• Conventionally, manual design of
  application-specific HDS for a given board.
• e.g. using Platform Builder of WindowCE
• SoC design require design space exploration for
  HW architectures to obtain optimal HW
  architecture(s).
• Each of HW architecture candidates require an
  application-specific HDS.
• Large number of candidate HW architectures
• manual HDS design is time-consuming.

15
Heterogeneous MPSoC DesignUnderstanding HW/SW
Complexity

• Orders of Magnitude
• MP Applications require different subsystem
  performances, e.g. VLC DCT in VideoCodec.
• Symmetrical MP induces sub-optional use of
  resources and/or performance overhead.
• Ad hoc architecture reduces number of processors.
• Key issue designing custom architecture.

16
Outline

• 1.- Programming Models the Bridge between
  Hardware and Software
• 2.- Application-Specific Programming Models to
  Handle MPSoC
• 3.- Programming Models at Different Abstraction
  Levels
• 4.- Next Generation Design Flow Based on
  Programming Models
• 5.- Summary

17
Classical Design FlowDiscontinuities
Fully implicit HW-SW interfaces
Fully explicit HW-SW interfaces
Binary
Binary
Software Sub
-
System
Software Sub
-
System
SW Appli
SW Appli
OS
HDS
Software
Software
Software
Software
Software
Software
Software
Software
HAL
HAL
Thread
1
Thread
1
Thread
1
Thread
1
Thread
1
Thread
1
Thread
1
Thread
1
ISS
IT Ctrl
ISS
IT Ctrl
FIFO
MEM
FIFO
MEM
Hardware
Hardware
SW Design
Hardware
Hardware
System Level
HW
HW
Virtual Prototype
Partition
Integration
GAP 1 Separate HW SW Design
Functional specification
ISA/RTL
HW Design
Design Cycle
18
Key Innovation for Higher than RTL DesignHW/SW
Interface Abstraction including CPU
19
Parallel Programming Models
SoC Design
Distributed SW Design
Programming Model
RTL (Verilog, BinSW)
Virtual Prototype (RTL HW, BinSW, e.g. SystemC)
MPI
RT-CORBA
CORBA SDL
Explicit concepts
All
HAL
Synchro- nisation
Communi- cation
- Concurrency - Threading
CPU imple- mentation
RTL HW CPU orga- nization
none
none
none

• New HW-SW Abstraction levels
• Hiding CPU in addition to HW SW

20
HW-SW Interfaces Abstractionfor SoC Design
System Architecture
Software Thread 1
Software Thread 2
Software Subsystem
Software Thread 1
Software Thread 2
HDS API
Hardware
HW
HW
21
Outline

• 1.- Programming Models the Bridge between
  Hardware and Software
• 2.- Application-Specific Programming Models to
  Handle MPSoC
• 3.- Programming Models at Different Abstraction
  Levels
• 4.- Next Generation Design Flow Based on
  Programming Models
• 5.- Summary

22
Perspectives HDS-CPU Codesign, New
Design/Synthesis Area
HW-SW Codesign
HDS-CPU Codesign
23
Application Example MPEG4
I
Input
Motion Estimate
Motion Compensate
DCT
Quant
VLC
Output
Video stream
Coded stream
P
Motion Prediction
Fn-1 (ref.)
P
IQuant
IDCT
I
Encoder Module
I
Transform Module
24
MPEG4 Architecture with Application Specific
HW-SW Interfaces
Application software encoder module
taskvlctask_behavior(),
Application software transform module
task1task_behavior(),
Hardware-dependent software switch_banks(),
wait_event(),
Hardware-dependent software
get_bank_address(), wait_event(),
SRAM
P1..4
SRAM
Pvlc
Ctrl
Ctrl
SRAM
NI
Hw
NI
Hw
CPU subsystem
CPU subsystem
DMA
Input
Video stream
Combiner
Coded Stream
25
HW-SW Interfaces for anMPEG4 Encoder
Video stream
Input
DIVX
VLC
Output
Bit stream
26
Summary Programming Models for SoC Design

• A necessity for higher than RTL design
• Need to be application-specific to reach cost and
  performances requirements
• Need new design automation techniques
• Is an opportunity to bring new HW-SW codesign
  approaches

27
Thank You