CSC205 Jeffrey N' Denenberg Lecture

1
CSC205 Jeffrey N. Denenberg Lecture 1

• Introduction, Logic Circuits

2
Administrative

• Handouts
• Course Syllabus (readings due before lecture)
• Lab Report Format
• Lab Assignment 1 (due next Tuesday 09/17)
• Grading
• 40 labs do prelabs on-time and do a good job on
  documentation (use a logic simulator to aid in
  documentation).
• 2 midterms (30) final (30)
• all labs and exams required no incompletes make
  arrangements in advance if you have a conflict.

3
Number Systems

• Radix 10 Why? (0, 1, 9)
• 5,273 5103 2102 7101 3100
• Binary Radix 2 (0,1)
• On/off
• 153 27 23 20 10001001
• Octal Radix 8 (0, 1, 7)
• 153 2 82 381 80 231
• Hexadecimal Radix 16 (0, 1, 9, A, F)
• 153 9161 9160 99

4
Complements(Representing Negative Numbers)

• Signed-magnitude Binary
• 9 00001001
• -9 10001001
• 1s complement (complement all bits)
• -9 11110110
• 2s complement (add 1 to the 1s complement)
• -9 11110111

0
000
-1
1
001
101
Sign bit
2
-2
010
101
3
-3
011
111
000
001
111
010
110
011
101
100
5
Other Codes

• BCD (10 4-bit binary codes per digit)
• Gray Code
• only one bit changes between adjacent Digits
• ASCII table 1-7

000
001
100
011
101
010
111
110
6
Digital Logic

• Binary system -- 0 1, LOW HIGH, negated and
  asserted.
• Basic building blocks -- AND, OR, NOT

7
Digital Logic Continued
8
Many representations of digital logic

• Transistor-levelcircuit diagrams
• Gate symbols (for simple elements)

9

• Truth tables
• Logic diagrams

10

• Prepackaged building blocks, e.g. multiplexer
• Equations Z S A S B

11

• Various hardware description languages
• ABEL
• VHDL
• Well start with gates and work our way up

12
Logic levels

• Undefined regionis inherent
• digital, not analog
• amplification, weak gt strong
• Switching threshold varies with voltage, temp,
  process, phase of the moon
• need noise margin
• The more you push the technology, the more
  analog it becomes.
• Logic voltage levels decreasing with process
• 5 -gt 3.3 -gt 2.5 -gt 1.8 V

13
MOS Transistors
Voltage-controlled resistance
PMOS
NMOS
14
CMOS Inverter
15
Switch model
16
Alternate transistor symbols
17
CMOS Gate Characteristics

• No DC current flow into MOS gate terminal
• However gate has capacitance gt current required
  for switching (CV2f power)
• No current in output structure, except during
  switching
• Both transistors partially on
• Power consumption related to frequency
• Slow input-signal rise times gt more power
• Symmetric output structure gt equally strong
  drive in LOW and HIGH states