Shift Registers

1
Shift Registers
A shift register shifts all bits one to the right
(or left) each clock period
?
?
?
?
0
0
?
?
?
1
1
0
?
?
0
0
1
0
?
0
0
0
1
0
1
1
0
0
1
1
Q0
Q1
Q2
Q3
Shift registers are useful for converting serial
(one bit at a time) data to parallel (multiple
bits at a time)
2
Ripple Counter
C2 C1 C0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
When one bit changes from one to zero, next bit
should toggle
A 3-bit asynchronous counter
Note the cumulative delays in changing of bits
3
Synchronous Counter
C2 C1 C0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
When previous bits are all ones, next bit should
toggle
A 3-bit synchronous counter
Note that all bits change at the same time
4
General Binary Counters
Q Count Value (Output)
D Parallel load value
LD Parallel load
CLR Set to zero
EN Count enable
Edge-triggered clock
Load and CLR may be synchronous or asynchronous
5
A Modulus N1 Counter
0,1,2,3,4,,N,0,1,2,
N
Whenever count gt N, clear counter
1
CLK
Requires synchronous clear
6
A Clock divider
Convert a 1MHz clock into a 1Hz clock by dividing
by 1,000,000
1,000,000
Count clock ticks ?When reach 1,000,000, clear
counter
1
1 Hz CLK
1 MHz CLK
Counter must have enough bits to reach compare
value (1,000,000)
7
A Balanced Clock divider
Convert a 1MHz clock into a 50 duty cycle 1Hz
clock by dividing by 500,000 and toggling output
500,000
1
2 Hz Unbalanced CLK
Toggle clock every 0.5s (500,000 clock cycles)
1 MHz CLK
1 Hz 50 d.c. clock
1 MHz CLK
8
VHDL for a simple counter
LIBRARY ieeeUSE ieee.std_logic_1164.allUSE
ieee.std_logic_unsigned.allENTITY count8
IS PORT( CLK IN STD_LOGIC EN IN
STD_LOGIC Q OUT STD_LOGIC_VECTOR(7
DOWNTO 0)) END count8
Inputs CLK and en Output Q (eight bits)
Note Need unsigned library to do math
ARCHITECTURE behavior OF count8 ISSIGNAL Count
STD_LOGIC_VECTOR(7 DOWNTO 0)) BEGIN PROCESS(CLK
) BEGIN IF RISING_EDGE(CLK) THEN IF
(EN1) THEN Count lt Count1
ELSE Count lt Count END IF
END IF END PROCESS Q lt Count END
behavior
Requires an internal signal for the count (cant
use the output Q for this)
If enabled, increment count if not, dont change
it
Assign the output (Q) the value of count
9
Synch and Asynch Controls
Add a synchronous load and an asynchronous clear
Note Entity not shown due to space limitations
ARCHITECTURE behavior OF count8LC ISSIGNAL
Count STD_LOGIC_VECTOR(7 DOWNTO 0))
BEGIN PROCESS(CLK,CLR) BEGIN IF (CLR1)
THEN Count lt 00000000 ELSIF
RISING_EDGE(CLK) THEN IF (LOAD 1)
THEN Count lt D ELSIF (EN1)
THEN Count lt Count 1 ELSE Count lt
Count END IF END IF END PROCESS Q lt
Count END behavior
Since CLR may come at any time, add to PROCESS
CLR is outside of check for rising edge
LOAD only happens on rising edge ? inside check
for rising edge