OnChip Inductance Extraction Concept

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On-Chip Inductance Extraction - Concept
Formulae 2002. 3Hyungsuk Kim
hyungsuk_at_cae.wisc.edu
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OutLine

• Introduction On-Chip Inductance
• Loop Inductance and Partial Inductance
• Closed Forms of Inductance Formulae
• Self Inductance Formulae
• - Hoer, FastHenry, Ruehli, Grover
• Mutual Inductance Formulae
• - Hoer (FastHenry), Ruehli, Grover
• Computational Results
• Conclusion

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Introduction On-Chip Inductance

• As the clock frequency grows fast, the reactance
  becomes larger for on-chip interconnections
• Z R jwL
• w is determined not by clock frequency itself but
  by clock edge
• w 1/(rising time)
• More layers are applied, wider conductors are
  used
• Wide conductor gt low resistance
• Multiple layer interconnections make complex
  return loops
• Inductance is defined in the closed loop in EM

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Loop Inductance

• Loop inductance is defined as
• the induced magnetic flux in the loop
• by the unit current in other loop

Ij
Loop i
Loop j
where, represents the magnetic flux
in loop i due to a current Ij in loop j

• The average magnetic flux can be
  calculated by magnetic vector potential Aij

where, ai represents a cross section of loop i
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Loop Inductance (contd)

• The magnetic vector potential A, defined by B
  A,
• has an integral form

• So, loop inductance is

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Partial Inductance

• Problems of loop inductance
• The loops (called return paths) are
• hardly defined explicitly in VLSI
• In most cases, the return paths
• are multiple
• Partial inductance
• proposed by A. Ruehli
• The return path is assumed at infinite
• for each conductor segment
• It can be directly appliable to circuit simulator
  like SPICE

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Partial Inductance (contd)
Loop inductance between loop i and j is
(assume loop i consists of K segments and loop j
does M segments) So, loop inductance is
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Partial Inductance (contd)

• Definition of partial inductance
• The sign of partial inductance is not considered
• So, partial inductance is solely dependent of
  conductor geometry
• Sign rule for partial inductance
• where, Skm 1 or 1
• The sign depends on the direction of current flow
  in the conductors

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Geometry and Formulae

• Conductor Geometry
• Inductance Formulae
• Self Inductance Grover(1962), Hoer(1965),
  Ruehli(1972), FastHenry(1994)
• Mutual Inductance Grover(1962),
  Hoer(FastHenry)(1965), Ruehli(1972)

x
z
Conductor 1
Conductor 2
Dz
Dx
y
Dy
(a) Single Conductor
(b) Two Parallel Conductors
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Self Inductance

• Grovers Formula

Grover 2 (without table)
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Self Inductance (contd)

• Hoers Formula

where
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Self Inductance (contd)

• Ruehlis Formula

where
If T/W lt 0.01
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Self Inductance (contd)

• FastHenrys Formula

where
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Comparisons of Self Inductance
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Mutual Inductance

• Ruehlis Formula
• Grovers Formula (single filament)

where
where
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Mutual Inductance (contd)

• Hoers Formula (multiple filaments)

where
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Conclusion

• On-Chip inductance becomes a troublemaker in
  high-performance VLSI design
• Higher clock frequency, wide interconnections,
  complex return paths
• The concept of partial inductance is useful in
  VLSI area
• Not related to the return path
• Only dependent of geometry
• Several inductance formulae are in hand but they
  have
• Different computational complexities
• Different applicable ranges according to the
  geometry