Interconnect Resource-Aware Placement for Hierarchical FPGAs - PowerPoint PPT Presentation

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Interconnect Resource-Aware Placement for Hierarchical FPGAs

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Count the number of interconnections,Nj,of length lj,from block vi ... Use gnl to create uniform complexity benchmarks circuits having values of Pd ... – PowerPoint PPT presentation

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Title: Interconnect Resource-Aware Placement for Hierarchical FPGAs


1
Interconnect Resource-Aware Placementfor
Hierarchical FPGAs
  • Amit Singh, Ganapathy Parthasarathy, Malgorzata
    Marek-SadowskaDepartment of Electrical and
    Computer Engineering University
  • of California, Santa Barbara, Santa Barbara, CA
    93106, USAICCAD 2001
  • Speaker??? 2004/04/09

2
Outline
  • Rents Rule
  • Rents Parameter
  • Local Rents Parameter
  • Application
  • Problem Definition
  • Logic Clustering using Rents rule
  • Placement using Rents rule
  • Experimental Results

3
Rents Rule
4
Rents Parameter
  • Rents Parameter
  • Is a measure of the interconnection complexity of
    the design
  • Allow us to choose the best physical architecture
    to implement the design
  • Rents Rule

5
Local Rents Parameter
  • Local Rents Parameter
  • Rents Rule doesnt reflect local fluctuations of
    the interconnection complexity in the design
  • For a placed circuit that minimizes the total
    wire-length, the Local Rents parameter of a
    design can be determined from the slope of the
    log-log plot of number of interconnections from a
    block versus length of interconnection (Net
    Length Distribution)
  • For a given block vi,
  • Count the number of interconnections,Nj,of length
    lj,from block vi
  • Find the best-fitting line on the log(Nj) versus
    log(lj)plot
  • Local Rents parameter gt slope of this log-log
    plot

6
Example
  • For a good placement in a D-dimensional
    Manhattan grid , the interconnection length
    distribution is of
  • the form

7
Application
8
Problem Definition
  • Given a hierarchical 2-D mesh FPGA chip with
    Rents parameter, Pa, and a design mapped to
    k-LUTs, having Rents parameter Pd,
  • Fit the design in the chip so that the area of
    the mapped, placed and routed design is
    minimized, subject to the constraint of a given
    bounding box aspect-ratio.

9
Hierarchical FPGA Architecture
10
Find the Rents parameter of hierarchical FPGA
architecture(Pa)
  • Find Pa
  • Use gnl to create uniform complexity benchmarks
    circuits having values of Pd ranging from 0.2 to
    0.9
  • Do a bottom-up clustering of blocks having a
    pre-defined Rents parameter(Pd)
  • Placement Routing
  • Measure the routing resource utilization
  • Find the value(Pd) that gives the highest network
    utilization

11
Example for Pa
12
Logic Clustering using Rents rule
  • A trial and error clustering and placement
    implementation method may lead to unnecessary
    congestion and too much unused routing resources
  • to alleviate this problem by depopulating logic
    clusters
  • Clustering technique guarantees
  • a fair amount of uniformity in the clustered
    designs complexity as measured by Rents
    parameter
  • gives our placement tool, a fairly uniform
    depopulated hierarchical circuit where the worst
    case Pd of any logic cluster is equal to Pa

13
Two Phases of Bottom-up Clustering
  • Find the upper bound on the cluster pin size
    based on Pa
  • Pd of any logic cluster in the design Pa
  • Clustering using modified T-VPack
  • Clustering based on the new set of cluster pin
    constraints

14
Placement using Rents rule
  • Simulated Annealing
  • Placement Cost Function
  • Using local Rents parameter
  • Recognizes the variations in the spatial
    complexities of the clusters and generates
    placement solutions which result in fewer routing
    tracks and shorter wirelengths after routing

15
Placement Cost Function
16
Experimental Results
13
21.3
9.4
17
Experimental Results
17.7
11
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