Embedded System Internal Representation ESIR

1
Embedded System Internal Representation (ESIR)

• Internal representation.
• SUIF Architecture Template Parallelism
  Support
• All tools operate on the ESIR, taking information
  from and storing results back into it.

2
Development of ESIR

• Defining annotations
• Annotations are data structures attached to nodes
  in the SUIF AST through pointers.
• Access to the ESIR will be provided through
  support functions
• Parallelism support
• Architecture template

3
Annotations in SUIF

• Means of extension in SUIF.
• All nodes in SUIF can have a list of annotations
  associated with them.
• They can be declared by any program and used to
  record information
• They contain two fields
• Name
• Data pointer (void )
• Can be written to and read from SUIF files.
• Structured annotations can have user defined
  structs.

4
Architecture Template

• Spec as structural VHDL
• Its role Arch info required by
• Estimator
• Partitioner
• Synthesizer
• Representation
• As a text file attached to SUIF
• Converted to the IR developed here at IIT in VHDL
  behv. synth. project..
• Support
• Functions to play with this representation

5
Parallelism Support

• Providing functions to tool developers to play
  around with ESIR.
• examples
• Building a communication graph
• setting/getting various information from the ESIR
• like mapping a function to HW or SW
• info on comunication
• Process specific information
• code size, threads related info

6
ESIR Example
7
Granularity of Partitioning

• Process level
• A complete process can be mapped to HW
• Function level
• Compute intensive functions mapped to HW
• Control /communication through software
• Evaluation criteria
• Support required at ESIR level
• Partitioner
• Synthesis, specially interface synthesis
• Efficiency ?

8
Open Issues

• More information required for development of
  ESIR from various tool developers
• partitioner
• estimators
• synthesis
• Granularity of partitioning
• Architectural template
• Restrictions in specification style and
  corresponding tool development

9
Overall Design Flow