IEEE Design Automation Standards Committee Plenary Meeting

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IEEE Design Automation Standards
CommitteePlenary Meeting

• Peter J. Ashenden, Ashenden DesignsDASC Vice
  Chairpeter_at_ashenden.com.au

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Agenda

• Previous Business
• P1596 ALF PAR approved
• VHDL-AMS Standard Packages Study Group approved
• Standards column in DTC Magazine
• Status Reports
• Any Other Business

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Status Reports (1)

• P1076 VHDL Analysis and Standards Group
• Issues Screening and Analysis Committee
• VHDL Programming Language Interface Task Force
• P1076.1 VHDL Analog and Mixed-Signal Working
  Group
• P1076.2 VHDL Math Package Working Group
• P1076.3 VHDL Synthesis Package Working Group
• P1076.4 Timing (VITAL) Working Group
• P1076.6 VHDL Synthesis Interoperability Working
  Group
• P1164 VHDL Multivalue Logic Packages Working
  Group
• P1577 Object Oriented VHDL Working Group
• Lib IEEE Study Group
• VHDL Microwave Study Group

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Status Reports (2)

• P1029 Waveform and Vector Exchange Working Group
• P1364 Verilog Working Group
• P 1364.1 Verilog Synthesis Subset Working Group
• P1481 Circuit Delay and Power Calculation Working
  Group
• P1499 Open Modeling Forum Working Group
• P1497 Standard Delay Format Working Group
• P1551 VHDL System and Interface based Design
  Working Group
• P1596 Advanced Library Format (ALF) Working Group
• OpenAccess Study Group