Addition

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Addition
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Definition of a binary adder
A binary adder with input length n is a
combinational circuit specified as follows
Claim the functionality of Adder(n) is well
defined.
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We show that for every An-10, Bn-10 and
C0 there exists Sn-10 and Cn such that
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Lower bounds on the cost and delay of
combinational circuits that implements Adder(n)
We would like to show a lower bound of linear
cost and logarithmic delay in n. Its suffices
to show that there exists at least one output, s,
of Adder(n) such that cone(s) n with respect
to Adder(n) .
We show that the cone size of the carry-out bit
Cn is 2n1.
Input bit Ai , 0 i n-1, is in the cone of
Cn
Set An-1i1 0n-i-1, Ai-10 0i , Bn-10
1n , and C0 0.
If Ai 0, then
Necessarily Cn 0, otherwise
a contradiction.
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If Ai 1, then
a contradiction.
Necessarily Cn 1, otherwise
By symmetry, every bit in the string Bn-10 is
also in the cone of Cn. The carry-in bit C0
is like A0, therefore C0 is also in the cone
of Cn.
Note that the same setting also proves
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Conditional Sum Adder CSA(n)
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Correctness Proof
The proof is by induction on n.
The induction basis, for n 1, follows directly
from the definition of a Full-Adder.
The induction hypothesis, for m lt n, is
Induction step, we prove for n
(1)
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(2a)
(2b)
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CSA(n) - Delay and Cost analysis under fan-out
limitations
Assume that n 2l and set k n/2,
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Master Theorem for recurrences provides
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We didnt take into account the fan-out of the
input gates. Is it justified in the case of
CSA(n)?
Cost Note that all input gates feed Full-Adder
circuits only. How much FAs are there in CSA(n)?
The fan-out of all input gates together is
T(n1.58).
The total cost needed for buffers is T(n1.58).
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Delay The MSBs An-1 and Bn-1 have the
maximum fan-out.
The input gates fan-out in the case of CLA(n) is
counted only once and it is at most

• To conclude, in CSA(n) design
• No change in cost asymptotics due to fan-out
  limitations.
• Quadratic increase in delay asymptotics due to
  fan-out limitations.