LECC 2002

1
CCU25

• Communication
• and
• Control Unit
• ASIC in CMOS 0.25 µm
• Ch.Paillard

2
SUMMARY

• CMS tracker slow control
• Network architecture and redundancy
• Messages structure
• CCU25 Bloc diagram
• Detail of Blocs I2C, parallel, memory, jtag,
  trigger
• Radiation hardness and irradiation test
• Conclusions

3
Tracker slow control
LD
APVs
Det
to DAQ
A/D
Memory
I V
A/D
DCU
PLL-Delay
Temp
FED
TTCrx
Front-end Module
Data Path
I2C
CLK T1
Control Path
LVDSMUX
CLK - T1
TTCrx
CCU
LVDS BUF
FEC ctrl
PCI Intfc
FEC
CCUM
In control room
On detector
4
RING
Internal protocol
Trigger
FEC
CCU
CCU
CCU
User accessible protocol I2C, Memory, Parallel,
JTAG
Application ASICs
Application ASICs
Application ASICs
5
Network architecture

• Ring protocol (Token-Ring)
• FEC-CCU (Front End Controller)
• CCU-CCU
• Message-based
• Broadcast
• Write post
• Read request
• Request packet

• Channel protocol
• CCU-Channels
• I2C, Jtag, Memory
• Parallel
• Data part
• Channel specific
• Asynchronous
• concurrent

6
Messages format
SOF EOF
TOKEN
SOF Destination Source Length Data CRC-16 EOF
CH TR Channel Specific command
CH TR CMD ADDR Data
I2C write
7
FUNCTIONS of CCU

• Communication
• Link between CCU FEC
• Token Ring network
• 2 line data and clock
• Data line NRZI
• Timing transport
• In clock line
• 7-bit address gt 127 ccu in ring

• Control
• Link between CCU F-E chips
• Several protocol
• 16 I2C master
• 1 JTAG master
• 1 memory
• 4 parallel interfaces

8
CCU25 Block diagram
Interrupts0-3
JTAG Master
JTAG Slave
Alarms
CLKI(A)
ST1
Trigger Decoder
Clock Distribution
ST2
CLKI(B)
ST3
ST4
CLKO(A)
Trigger Counter other timing logic
DO(A)
Reset
Link Controller
Node Controller
DI(A)
CLKO(B)
DO(B)
SCL SDATA
I2C Master
DI(B)
16 x I2C Buses
Memory Bus Interface
Ext Reset
Parallel interface
I2C Master
D07 A015 R/W CS1-2
PA07 PB07 PC07 PD07
Local Bus
9
Node Controller

• Control network channels
• Control Register (5)
• Select net Input A-B
• Select Output A-B
• Enable channels
• Reset channel
• Alarm
• External reset out

• Status register (6)
• Illegal sequence
• Crc error
• Invalid command
• I2C busy
• Parity error counter
• Transaction number

10
I2C Interface

• 2 wires clock, data
• Read-write
• 7-bit addr, 8-bit data
• 10-bit addr, 8-bit data
• APV6 mode
• Read-mod-Write
• and, or, xor

• Status registers
• Detection of line data low
• Invalid command
• Transaction last succ.
• Transaction last bad
• Last command
• Control register
• Clock freq. 100,200,400,1000 Khz
• Write acknowledgement or not
• mask

11
Memory Interface

• 16-bit addr., 8-bit data
• 2 windows pre-decoded
• Block transfer
• Read mod. write
• and, or, xor

• Status registers
• Inv. Command
• Inv. Address
• Control registers
• Length chip select
• Windows 1 2
• Enable w1 et w2

12
Parallel Interface

• 8-bit bi-dir
• Each bit individually
• Input strobe
• Tr ou level
• interrupt
• Output strobe
• 100ns,200ns,400ns,1µs

• Status registers
• Interrupt
• Inv. Command
• Control registers
• Strobe 100,200,500,1000 ns
• Enable interrupt

13
JTAG MASTER

• Simplified JTAG master
• TCK, TMS, TDO out, TDI in
• No command structure
• Need special ring packet
• Example of data part message

TMS118 TDO118 TMS74 TDO74 TMS30 TDO30
14
Trigger

• Distribution of ST1-ST4
• ST1- ST4 output can be delayed (1-16) clock
  period
• 4 Counters 32-bit
• 2 LVDS input T1 and Clock

25 ns
CLK
T1
CLKT1
15
Redundancy
16
RadiationHardness and irradiation

• For total dose tolerance
• Library of standard cells rad-tolerant 0.25 µm
  CMOS
• For SEU robustness
• One-hot type state machine
• Node controller 3 blocks majority voting
• Parity on all registers
• Error counter
• Irradiation
• Test at PSI 300 MeV proton beam 3x108 p/s
• 4.5 SEU/chip/hour gt LHC 4.21x10-2 SEU/chip/hour

17
CCU_M
photo
18
CCU25 layout

• Synthesis from HDL
• Features
• 6x6 mm2, 3 metals
• 196 pin fpBGA
• array 14x14 with 1mm pitch
• 250 mW _at_ 2.5v

19
CONCLUSIONS

• Network interface (Like Token Ring) 40 Mb/s
• Control interface
• I2C, parallel, memory bus and JTAG.
• Radiation resistant