Superscalar Processors

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Superscalar Processors
Presented by Jeffery Aguiar
(Pictured above is the DEC Alpha 21064)
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Presentation Outline

• Purpose
• Theory
• Design
• Implementation
• Evaluation
• Conclusion

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Purpose

• Improve chip productivity
• Reward the market with increased processor
  scalability
• Develop without replacing current code
  compilers
• Optimize logic architecture

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History

• Motivation Complete multiple instructions per
  clock cycle to decrease ALU idle time
• Employ multiple ALUs FPUs to execute
  instructions
• Reason why RISC over took CISC in the mid-1990s
• Quick facts
• First implementation Seymour Crays CDC 6600
• All CPUs since 1998 are considered superscalar

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Theory

• Parallelism - multiple pipelines
• Fundamental Processor Units (FPU)
• Improves upon current techology
• Dependency
• Example code segments
• Dependent
  Independent
• A B C
  x y z
• C A D
  n k p

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Design

• Fetch multiple instructions
• Decode/Evaluate dependencies
• Reorder code segment
• Execute
• Schematic

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Example PowerPC

• Apple Macintosh G5 (IBM 970FX chipset)
• Vector Processing Unit (VPU) block diagram

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Evaluation

• Weaknesses
• Dependencies (video games)
• Branch prediction is tricky business
• Strengths
• Independent variables
• Strong basis in logic (video rendering)

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Conclusions

• Multiple instructions executed per cycle
• Logic approach with hardware backing
• One variable of the performance metric
• Complicated when dealing with dependency

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References

• Smith, James. The Microarchitecture of
  Superscalar Processors
• L. Gwennap, PPC 604 Powers Past Pentium,
  Microprocessor Report, pp. 5-8, Apr. 18, 1994.
• J. K. F. Lee and A. J. Smith, Branch Prediction
  Strategies and Branch Target Buffer Design,
  IEEE Computer, vol. 17, pp. 6-22, January 1984.

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Questions ?