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DFM Foundry platform

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Active, poly and metal shorts and opens due to particle ... Material shorts. Random Yield Loss: Test Structures. Extract Metal layer open and short defectivity ... – PowerPoint PPT presentation

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Title: DFM Foundry platform


1
(No Transcript)
2
An Effective DFM Strategy Requires Accurate
Process and IP Pre-Characterization
  • Carlo Guardiani, Massimo Bertoletti, Nicola
    Dragone, Marco Malcotti, and Patrick McNamara
  • PDF Solutions Inc.
  • DAC 2005, Anaheim, CA

3
Technology Roadmap Challenges
  • 45nm
  • Lithography
  • Layout pattern dependence
  • Immersion litho,
  • OPC/PSM integration w/ photo window
  • Front end/Transistor
  • New gate/oxide architectures
  • Reliability
  • 65nm
  • Lithography
  • OPC/PSM integr. w/ photo-window
  • Front-end/Transistor
  • Layout dependent performance
  • Parametric variation
  • 90nm
  • Back-end integration
  • Low-k
  • CMP
  • Product ramp issues
  • Yield vs. performance

4
The Evolution of Product Yields
  • Random defects are no longer the dominant yield
    loss mechanism
  • Yields are limited by design features

5
From Reactive to Proactive DFM A Copernican
Revolution
Yield Revolved Around Rules
  • Design rules guarantee yield!well, not really
  • then recommended rules
  • and opportunistic design data base
    post-processing to enforce them

Yield Models are the driving force in the DFM
universe
  • Accurate Yield Models Characterizedin Silicon
  • Fully integrated in standard design tools and
    flows

6
Rule-based DFM?
7
Reactive vs. Proactive DFM
Reactive DFM
DRM
SPICE
Pro-Active DFM
Manufacturing Facility
DRM
SPICE
8
Proactive DFM
  • Designer access to process data is limited
  • DFM today is Reactive
  • Increased design cycle time
  • Risky design feature changes
  • Misaligned mask GDSII and design database
  • DFM needs to be Proactive
  • Up-front accurate process characterization
  • Occurring early in the design flow
  • Model based IP characterization
  • Manufacturable-by-construction designs

9
DFM characterization Of IP libraries
  • Characterize IP library for yield (.pdfm)
  • Extract design attributes of yield models
  • Include random, design systematic andlitho
    effects
  • New yield library view (.pdfm)
  • Enable hierarchical large capacity DFM chip
    analysis

10
Random Yield Loss Physical Mechanisms
Material opens
Material shorts
Yield Loss Mechanisms
Type
Active, poly and metal shorts and opens due to
particle defects
Random
Contact and via opens due to formation defectivity
11
Random Yield Loss Test Structures
  • Extract Metal layer open and short Defect Size
    Distribution (DSD)
  • Extract Metal layer open and short defectivity

12
Systematic Yield Loss Physical Mechanisms
Yield Loss Mechanisms
Type
Impact of micro/macro loading design rule
marginalities
Systematic
Leakage from STI related stress
Contact/via opens due to local neighborhood
effects (e.g. pitch/hole size)
Misalignment, line-ends/borders
13
Systematic Yield Loss Test Structures
Without Neighborhood
With Neighborhood
14
Printability Yield Loss Physical Mechanisms
Yield Loss Mechanisms
Type
Poor contact coverage due to misalignment and
defocus/pull back
Systematic
Poly/Metal shorts
Material opens
15
Printability Yield Loss Modeling
Layout Metric
Misalignment
Mask Error
Defocus
Exposure
Yield Loss
coverage
16
The .pdfm View
  • Library characterized to generate
    manufacturability view (.pdfm)
  • Random and design systematic yield
  • Litho process window
  • Using calibrated yield models
  • Multi-layer litho process window incorporated

Cell Characteristic Library View

Lay out GDS
Schematic SPICE Netlist
PR Footprint LEF
Performance .lib
Logic Function Verilog
Power
Noise

Manufacturability .pDFM
17
Application IP library DFM Quality Analysis
  • Yield sensitivity analysis
  • Optimal design depends on process corner
  • Ex NAND2 Y5, Y6, Y1, Y4
  • Best becomes worst at different process corner
  • Ex NAND2 Y1_m1opens vs. Y1_m1shorts
  • DFM Sensitivity depends on layout attributes
  • M1 more sensitive than Poly
  • Identify redundant layout implementations
  • Ex AOI Y4, Y5

NAND2 CELL
Dominant Process Effect
AOI CELL
Process Corner
18
Yield aware synthesys and placeroute
RTL Design
Hierarchical Floorplan
DFM SW plug-ins
Yield View (.pdfm)
VERIFICATION
Yield Gap
Yield
Yield Models
Models
Estimator
Estimation
Physical Synthesis
Yield
Yield
Extended IP
DFM LIBRARIES
Optimizer
Optimization
Chip Assembly
Sign-off
Standard Libraries
  • Proactive DFM
  • Maximize manufacturability by construction

19
Conclusions
  • Impact of design systematic and lithography yield
    loss mechanisms crossed over random phenomena
  • Rule-based, reactive DFM is impractical
  • Model-based, proactive DFM is the answer
  • Early in the design flow
  • Find the best trade-off based on actual process
    capabilities
  • Before verification
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