Topic 3: Synchronous Logic Problems and Asynchronous Logic System Level Design

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Topic 3Synchronous Logic Problems and
Asynchronous Logic System Level Design

• SFSU ENGR 852
• Fall 2003
• 2/17

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ResourcesAsynchronous Logic Introduction

• http//www.cs.man.ac.uk/async/background/
• "The Return of Asynchronous Logic
• http//www.cs.columbia.edu/async/misc/technologyre
  view_oct_01_2001.html

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Synchronous Logic Problems

• Clock Period Set for Worst Case
• Sensitive to Clock Skew
• Sensitive to Process Variation
• Metastability a Problem. Bounded Response Time.
• Power Used Each Clock Tick
• Difficult to Migrate Technologies

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Synchronous Logic Problem 1 Clock Period Set for
Worst Case

• Clock Period 40ns

Logic Block Tp5ns
0 10ns 20ns 30ns 40ns
50ns 60ns 70ns 80ns 90ns
100ns
CLK
D1
Q1
D2
Q2
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Synchronous Logic Problem 1 Clock Period Set for
Worst Case

• Clock Period 4ns

Logic Block Tp5ns
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Synchronous Logic Problem 1 Clock Period Set for
Worst Case

• Clock Period Must be Greater Than Delay Between
  Any Two Flip-Flops.
• Whats the Minimum Clock Period? ?25ns

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Synchronous Logic Problem 2 Sensitive to Clock
Skew

• Clock Period Period8ns, Clk1 Clk2

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Synchronous Logic Problem 2 Sensitive to Clock
Skew

• Clock Period Clk2 Delayed

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Synchronous Logic Problem 2 Sensitive to Clock
Skew

• Clock Period Clk1 Delayed

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Synchronous Logic Problem 3 Sensitive to Process
Variation

• Process Variations Affect Speed
• Slight Variations in Size
• Slight Variation in Doping

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Synchronous Logic Problem 4 Metastability a
Problem. Bounded Response Time.

• Metastability A Confused Circuit. It Doesnt
  Know What to Output.
• Example In a System Where 1 is Represented by
  5V, 0 is Represented by 0V, and the Input Value
  is 2.5V, Whats the Q Value Below?

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Synchronous Logic Problem 4 Metastability a
Problem. Bounded Response Time.
CLK
D(2.5V)
Q (0?1)
OR
Q (0?0)
OR
Q (1?0)
OR
Q (1?1)
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Synchronous Logic Problem 4 Metastability a
Problem. Bounded Response Time.

• Metastability Means Increased Delay From Time
  Clock Ticks Until Q Changes (Response Time)
  ?Logic Delay Looks Bigger ?Clock Must Be Run
  Slower.
• Not Robust When Inputs Come From External Source
  (May Catch Signal on Transition)

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Synchronous Logic Problem 56Power Used Each
Clock Tick Difficult to Migrate Technologies

• Power Dissipation Happens on 0?1 Transitions.
  Clock ALWAYS Switching.
• Migration to New Technology Often Requires all
  System Components to be Migrated to New
  Technology.

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Asynchronous Solution

• All of These Problems Would be Solved if Logic
  Didnt Depend on a Clock. If a Logic Block Could
  Take All the Time it Needed to Finish Then Tell
  the Next Logic Block that Hey, Im Finished. Go
  Ahead, a Clock Wouldnt be Necessary.

Im Done, Go Ahead!
Logic Block 2 25ns
Logic Block 1 5ns
Data
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Question

• Why Are we Looking at Logic Between Flip-Flops?
• Because we See That Pattern
• 1.
• 2.

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Asynchronous Logic

• Self-Timed, Pipelined System

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Asynchronous Logic

• Handshaking Protocol Signal Meanings
• High Req0 Block0 Has Finished. Request to
  Block1to Start Processing Data. (Block1 Will Only
  Start When it Becomes Free and Has Stored data
  See Below).
• High Ack0 Block1 Has Stored Input Values into
  FF1 and is Processing Data. Block0 Can Destroy
  Input Data.
• High Start1 Grab Input Data
• High Done1 Block1 Logic Has Finished.

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Asynchronous Logic
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Asynchronous Logic

• What Happens With 5ns 25ns Blocks Now?

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Asynchronous LogicFour-Phase Handshaking Protocol
Req0 Start1 Ack0 Done1 Req1 Start2 Ack1 Done2
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Another Question

• What Kind of Logic is the Handshaking Manager?
  Can it be Implemented in Combinational Logic?

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How to Calculate Combinational Logic Delay
http//us.st.com/stonline/books/pdf/docs/1879.pdf
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How to Calculate Combinational Logic Delay
http//us.st.com/stonline/books/pdf/docs/1879.pdf