eVIKINGS II Meeting

1
Design and Testof Digital Systems
Raimund Ubar Tallinn Technical University raiub_at_pl
d.ttu.ee
2
Roadmaps

• International Technology roadmap for
  semiconductors
• MEDEA Industry-driven pan-European programme for
  advanced co-operative RD in microelectronics
• A dependability roadmap for the information
  society in Europe

3
System Design at a Crossroad

• Productivity Crisis
• 21 Productivity Increase / Year vs.
• 58 Complexity Incease / Year

4
Electronic Design Automation (EDA)

• System on a Chip development Yesterdays chip
  is todays functional block!

New design methodologies are needed
5
Technology trends
6
Impact of new design technologies on cost
Tall thin engineer
Large block reuse
Intelligent test bench
7
Landscape of design technology
8
EDA challenges

• Designers need to increase the level of
  abstraction, because the amount of information in
  the designs exceeds their ability to track the
  information? increased use of synthesis
  technologies
• Necessity to reuse already designed, tested and
  synthesised functional blocks ? Intellectual
  Property (IP)
• Validation High-Performance simulation tools for
  the entire design are needed (including early
  high-level timing validation)
• Improvement of the cooperation of different
  EDA-tools? Standards have to be defined

9
FW 6 - EuroSoC Key Nodes

• Network on chip (Hannu Tenhunen, Sweden)
• Multiphysics (Marta Rencz, Hungary)
• Mixed signals (JoseLuis Huertas, Spain)
• Low power (Christian Piguet, Switzerland)
• Integrated intelligence (Patrick Dewilde, The
  Netherlands)
• Test and debug (Ch. Landrault, France)
• Formal mehtods (Dominique Borrione, France)

10
FV 6 - EuroSoC Key Nodes

• Modeling (Alain Vachoux, Switzerland)
• Reconfigurable SoC (W. Rosenstiel, Germany T.
  Arslan, UK)
• Design methods and IP reuse (J. Vounckx, Belgium
  J.C. Lopez, Spain)
• SoC programming model (E. Villar, Spain)
• SoC application (N. Wehn, U. Germany L.Lavagno,
  Italy)
• SoC education (J. Madsen, Denmark)

11
EuroSoC Thematic Areas in Test

• Research topics
• Digital, Analog, Mixed-Signal, and RF
• Failure Analysis, Defect and Fault Modeling
• ATPG, BIST, DFT
• Test Synthesis , Test Resource Partitioning and
  Embedded Test
• Defect/Fault Tolerance and Reliability
• Debug and Diagnosis
• Research communities
• European Group of the IEEE Test Technology
  Technical Council
• International Test Conference (ITC), VLSI Test
  Symposium (VTS)
• European Test Workshop (ETW), DATE C, Online Test
  Symposium (IOLTS)

12
Paradigm Shift in Test

• Sky-rocketing complexities with decreasing
  pin/gate ratio, higher frequencies and decreasing
  product life cycles
• New defects due to technology evolution
• Hardware/software designs, test of programmable
  systems
• IP(core)-based designs
• Increasing use of analog, mixed-signal and RF IPs
  
• Increase of temporary faults (transient and
  timing faults)

13
Current Status and Barriers to Overcome

• Current status
• Testing cost may represent up to 50 of the
  manufacturing cost of SoC
• Some of the barriers
• Development of nanometer fault models
• ATPG, BIST for real defects
• Reduction of test execution time
• Power consumption during test
• Optimized Test Resource Partitioning strategies
• Obsolescence of Iddq testing
• Analog BIST
• Tolerance of temporary faults
• DfD methodology

14
Testing and Quality
How much to test?
The problem of testing can only be contained not
solved T.Williams
15
Complexity vs. Quality

• Problems
• Traditional low-level test generation and fault
  simulation methods have lost their importance
  because of the complexity reasons
• Traditional Stuck-at Fault (SAF) model does not
  quarantee the quality for deep-submicron
  technologies

16
Complexity vs. Quality

• New solutions
• The complexity is handled by raising the
  abstraction levels from gate to
  register-transfer, instruction set architecture
  (ISA) and behavioral levels
• But this moves us even more away from the real
  life of defects (!)
• To handle adequately defects in deep-submicron
  technologies, new fault models and
  defect-oriented test generation methods should be
  used
• But, this is increasing even more the complexity
  (!)
• To get out from the deadlock, the both trends
  should be merged into hierarchical approaches

17
Research in TTU (ATI)

• Modeling of Digital Systems at different levels
  to cope with the complexity
• Test generation and fault simulation
• Hierarchical approaches to test generation and
  fault simulation
• Intensive international cooperation
• Joint design and test flow methods and tools
  (integr. research at ATI)
• BIST (cooper. with U Stuttgart, Uni Linköping,
  Artec Design)
• Defect-based approach (cooper. With TU Warsaw,
  Slovak Academy)
• Collaborative design via Internet (Fraunhofer
  Inst. In Germany)
• New teaching methods, tools, research scenarios
  (TU Ilmenau)
• Subcontractors in red

18
DECIDER Hierarchical ATPG
Modules or subcircuits are represented as
word-level Decision Diagrams
19
Joint VHDL Design and Test Flow
Cooperation with LIU (subcontractor) and in TTU

• High-level synthesis
• CAMAD developed at Linköping University
• Test pattern generation
• DECIDER developed at Tallinn Technical University
• Interfaces to
• behavioral and RT-level VHDL and
• EDIF netlist formats

20
BIST (Optimization and Hybrid Solutions)
Cooperation with LIU (subcontractor)

• Combining
• on-line generated pseudo-random patterns
• with pre-generated and stored test patterns
• Problems
• To find the best characteristics for test
  generator (PRPG)
• To find the best level of mixing pseudo-random
  test and stored test as the tradeoff between
  memory cost and testing time

SoC
ROM
. . .
Core
Test Generator
.
CORE UNDER TEST
Controller
Response Analyzer
21
International Virtual Lab Tool integration
Cooperation with EAS/IIS, Dresden EV-subcontractor
22
Tools for test generation and fault simulation
Methods Single fault Parallel Deductive
Fault models Stuck-at-faults Stuck-opens Delay
faults
Methods Deterministic Random Genetic
Levels Gate Macro
Test Generation
Fault Simulation
Fault Location
Design
Test
BIST Simulation
Methods BILBO CSTP Store/Generate
Fault Table
Fault Diagnosis
Test Optimization
23
Applets for Learning RT Level Test
Cooperation with TU Ilmenau, Germany EV
subcontractor

• For learning problems of RT-level design and
  test
• - Design
• - Simulation
• - Fault simulation
• - Test generation
• - DFT
• - BIST

24
Conclusions

• Long term goal of the NoE EuroSoC in Framework 6

2003
2005
2007
2010
Get funding from second FP6 Call and other
public funding
Start
Convince industry to partially fund the network
Network Fully funded by Industry