A NEW GRAPH STRUCTURE FOR HARDWARE-SOFTWARE PARTITIONING OF HETEROGENEOUS SYSTEMS

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A NEW GRAPH STRUCTURE FOR HARDWARE-SOFTWARE
PARTITIONING OF HETEROGENEOUS SYSTEMS

• G. N. Khan and M. Jin
• System-on-Chip Research Group
• Electrical Computer Engineering
• Ryerson University, Toronto ON M5B 2K3

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Hardware-Software (HW/SW) Co-design

• Objective
• To design HW/SW early in the design cycle to
  produce more reliable, efficient and first time
  right design with in a reasonable time.

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Hardware Software Partitioning

• Assignment of System parts to hetrogeneous
  implementation units (Hardware and Software)
• Meet constraints (Timing) and Minimize cost
  (Area, Time to Market)
• Directly affects the cost and performance of
  final system

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Specification

• Traditionally in Plain English
• MSC, SDL, SystemC were developed
• Both textual and graphical representation like
  DAG (Directed Acyclic Graph) are used to describe
  system.

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What is DADGP

• Directed Acyclic Data dependency Graph with
  Precedence is an extension of DAG
• DADGP is a super set of DAG
• Two types of edges
• 1) Weighted Dependency edge
• 2) Precedence edge

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DADGP Example

• Arrow represents dependence relationship
• Precedence edge is represented with a line
• Precedence dependency captures the order of
  execution between nodes and such nodes can be
  executed in parallel.
• Only necessary parallelism is exposed

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Overall System Partitioning Structure
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System Partitioning Algorithm

• Profiling and building an initial DADGP
• Find the LD_path (longest delay path) in DADGP
• Mapping of LD-path nodes to hardware
• Schedule and if invalid mapping then goto Step
  iii
• Update DADGP and calculate the total execution
  time of target system.
• If system constraints (specified by the user) are
  not met then goto Step ii, otherwise quit.

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Profiling

• Profiler collects the following data
• Execution time
• Amount of data transfer
• Execution order
• Data dependencies between nodes

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Longest Delay Path Search

• Finding the longest delay path in DADGP is like
  finding a bottleneck of the system
• Minimizes search space for mapping
• Longest Delay path means, longest execution path

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Mapping

• Maps a node to be hardware
• Mapping can change the Longest Delay path, as
  well as DADGP
• Mapping is valid if mapping that node to Hardware
  gives the shortest Longest Delay path

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Scheduling

• Very simple List Scheduling approach.
• Schedules the earliest node first without
  violating the resource limit.
• Exposes parallelism and changes the DADGP
  accordingly.

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Summary of DADGP Scheduling

• Start scheduling from the root of DADGP
• Traverse down the tree and schedule the earliest
  starting time node
• If the node is connected with precedence
  dependency edge, check whether exposing
  parallelism can eliminate that edge. When an
  edge is eliminated, DADGP structure may convert
  to two DADGPs. Roots of the two DADGPs are
  combined to form a single DADGP with a dummy root
  node.
• In case of multiple descendents, schedule them
  forcibly by adding PEs
• Update the PE resource (HW-SW) library

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Constraints

• Constraints of deadline and cost is given by the
  designer.
• Hardware cost is calculated by gate count.
• Different granularity level should be explored if
  no solution is found.

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Edge Detection Example

• Pair of 3x3 masks are convolved to estimate
  gradients (Gx Gy) in x and y directions
• HW-SW Library

Gx
Precedence dependency
Gy
Operation SW EXE (ms) HW EXE (ms) HW Area (gates)
Gradient (Gx or Gy) 9.4 1.4 1200
Square 5.2 0.9 500
Add 3.88 0.3 100
Gx2
Data dependency
Gy2
Add
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Edge Detection Solutions
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Performance improvement vs. HW area
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Conclusion

• HW-SW Partitioning is a NP-hard problem
• To find optimal partitioning Hardware-Software
  set is very difficult due to many factors
  affecting the partitioning decision.
• DADGP Structure Expose Parallelism
• The complexity of DADGP partitioning algorithm is
  approximately n2log(n).