Team Market A Synthesis of Catastrophe Final Class Presentation PowerPoint PPT Presentation

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Title: Team Market A Synthesis of Catastrophe Final Class Presentation


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Team MarketA Synthesis of Catastrophe Final
Class Presentation
Kermin Fleming Ka Wing Ho Jonathan Wilson Naju
Mancheril
2
  • In the beginning was the plan,and then the
    specificationAnd the plan was without form,and
    the specification was void.
  • --Dictionary.com snafu principle

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Review of Design Goals
  • Original Design Goals
  • Support LCD display interface X
  • Decided LCD Display was redundant by DR2
  • Dangerous virus voice warning v
  • Cope with garbled/distorted signals ?
  • Advanced Signal Processing found to be too
    ambitious by DR2. Testing still pending.
  • Final Design
  • Voice warning is implemented
  • Added Features Voice Identification of ALL
    viruses name, not just dangerous ones.

4
Changes in architecture
  • No More SRAM
  • Original idea store decoded audio data
  • Problem reads from SRAM and subsequent
    asynchronous transmission too slow for real-time
    play back
  • Solution 1 Need 64KB. DSP has 32KB, ARM has
    32KB. Store ½ of the processed data on DSP and
    put the rest on ARM
  • Real-time audio playback works but

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Changes in architecture cont
  • No More SRAM
  • Original idea store decoded audio data
  • Problem Dealing with file halves is hard to
    manage, system is difficult to debug, more
    interconnections.
  • Solution 2 Need 64KB. NIOS has 100KB. Use NIOS
    to buffer decoded audio file.
  • Real-time audio playback works.

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Changes in architecture cont
  • No multiple custom cores
  • Original Idea multiple parallel cores connected.
  • Problem arbitration difficult, FPGA timing
    difficult.
  • Solution Turns out that if we hand off a task
    to hardware, its done by the next cycle! Simply
    have a single hardware string matcher.
  • Run findHits() on a single database string and
    8000 neighbor words in 8030 NIOS cycles.

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System Architecture
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DSP Card
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NIOS
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NIOS-Hardware Interface
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String Matcher
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ARM
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Performance
Run time includes time to playback audio
encoding 3 times.
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War Stories
  • Naju Write Once Memory
  • Elliott Scriveners Tale
  • Michael Matlab C
  • Jon Wilsons Tearjerker

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The Atmel Chip Motivation
  • Need to store CELP audio files for every virus in
    the 2MB database Flash chip
  • Need to latch address bits since we dont have
    that many pins to give up.
  • Basic operations
  • flashread(), flashwrite(), flasherase()
  • flashwrite() works sometimes.

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The Atmel Chip The Odyssey
  • Time
  • 1 day to wire-wrap latch (Elliot and Jon) and
    verify that it works with 5 NOP delay.
  • 1 day to realize Flash chip was broken.
  • 1 day to test new Flash chip.
  • 1 day to realize all Flash chips are broken.
  • 2 days to fix the Flash access functions, load
    and store CELP files, and add Flash-programming
    mode to server.

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The Atmel Chip Lessons Learned
  • You can never spend too much time testing
    hardware. This is especially true when you
    consider spontaneous combustion.
  • Maybe almost correct is good enough
  • What saves us is error correction during decode.

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The Scriveners Tale
  • It was a dark and stormy night
  • A frustrated engineer and a DSP card sat alone
    together
  • One was about to go flying out the window
  • Learning about the DSP was hard
  • Poor/hard to find documentation
  • Whats that linker do, anyway?
  • Lots of technical issues/quirks
  • Them jumpers sure are purty.
  • Can you hear me now? Why are there on board mics?
  • Oh no! the interrupts didnt clear!
  • Livelock??? Whats that?
  • Hey Wilson, shouldnt that be a lt?
  • Do you think the codec does sign-extension?
  • Manuals dont always tell the whole story ?
  • Vocoder 100, DSP 64
  • Last minute architecture changes

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Stupid Bug
  • Looks easy
  • Port the code from Matlab to C
  • Code seems to workmost of the time ?!
  • Subtle difference in semantics between different
    programming languages
  • Research code Matlab, SML, Modula3???
  • Embedded System C, C, Java

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Matlab and C
  • Matlab vector or matrix
  • qry_seq qry_str(best_qry_lbest_qry_r)
  • db_seq db_str(best_db_lbest_db_r)
  • best_score b62_score(qry_seq,db_seq)
  • C pointers
  • best_score b62_score(char qry_s, char db_s)
  • Seems to be right ???
  • No!!!!
  • qry_str(best_qry_lbest_qry_r) means the subset
    of the char vector starting from index best_qry_l
    to best_qry_r !!!!
  • Something is missing..the LENGTH
  • Possible solution b62_score(char qry_s, char
    db_s, int len)

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Other Gotcha
  • Notice that the length cannot be hardcoded to be
    3
  • Trim right and Trim left in the Matlab code means
    the length can actually varies from 1 to 3.
  • Others
  • Array indexing
  • Matlab starts from 1
  • C usually starts from 0
  • Summary
  • Make sure your assumption is correct when porting
    code from one language to the other (or from one
    platform to the other).
  • Do extensive unit testing before code integration

22
Wilsons Tearjerker
  • Importance of personalities in a group
  • I dislike all-nighters
  • The others in my group seemed to love them
  • Who is right? Should we stay up all night or
    spread our work out evenly? Must we choose?

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Group Dynamics
  • The answer is compromise!
  • I stayed up late on some occasions
  • But we also worked during the day in effective
    blocks of time
  • This would not have been possible without
    communication with the group
  • Dont let those bad sentiments boil up be sure
    to voice your opinion

24
SoC Design (Motivation)
  • Integrated circuits are small, cheap, fast, and
    virtually indestructible after fabrication.
  • Why redesign a DSP when we can drop in n DSP
    cores?
  • Co-design hardware and software for system.
  • Explore various designs, evaluating performance,
    identifying bottlenecks and cost.

25
SoC Design (Reality)
  • Every off-board chip we had burned out at least
    once many more than once.
  • Although we have some freedom in designing
    hardware and software, changing a simply serial
    4-phase handshake interface can take hours.
  • Performance is not easy to measure even if you
    know the average case.

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SoC Design (Ideal)
  • Lets actually simulate. No hardware until we are
    done testing and measuring performance and even
    then, wire-wrap.
  • Standard interface from one component to another
    (simply configure bus width).
  • IDEs that dont work against you.
  • (Correct) meaningful documentation. Just ask the
    NIOS people how its done.

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  • QUESTIONS ?
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