Summiteers Marketing Plan Proposal

1
Computer Organization Prepared by Anh Q.
Vu Course CS-147 Professor Sin-Min
Lee Date Summer - 2001
2
Computer Organization

• Contents (Text Book page 142 158)
• Overview
• Computer Organization
• Definitions - Buses
• Computer Organization Diagram
• CPU organization Diagram
• Memory
• Memory Chip Organization
• The Instruction Cycle
• Supporting Diagrams
• (25 minutes)

3
Computer OrganizationOverview

• The Intel Microprocessor Evolution
• Microprocessor Year introduced of
  Transistors
• 8008 1972 3000
• 8080 1974 4500
• 8085 1976 6500
• 8086 1978 29,000
• 8088 1979 29,000
• 80286 1982 130,000
• 80386 1985 275,000
• 80486 1989 1.2 million
• Pentium 1992 3.1 million
• Pentium Pro 1995 5.5 million
• Pentium III 1999 9.5 million
• Pentium 4 2000 42 million

4
Computer Organization
5
Computer Organization

• A computer is organized into 3 internal parts
• CPU
• Memory
• I/O (Input/Output)

6
Computer Organization

• CPU
• It is the Central Processing Unit of the
  computer.
• Its function is to execute or process the
  information stored in memory.
• The CPU is connected to memory and I/O through
  strips of wire called bus.

7
Computer Organization

• 2. Memory
• Memory is the big store house of data located
  within the main computer outside of the
  Microprocessor.

8
Computer Organization

• 3. I/O (Input/Output)
• Input devices provide signals to the CPU.
• Keyboard, Sensors, Switches, etc.
• Output devices take signals from the CPU and
  perform required actions.
• Printers, Monitor, Lights, etc.

9
Computer OrganizationBUS

• Bus
• Bus is a set of wires that connects the CPU to
  memory and I/O
• It carries information from place to place just
  as a street bus carries people from place to
  place.
• There are 3 types of bus
• Address bus
• Data bus
• Control bus

10
Computer OrganizationBUS cont.

• a) Address bus
• Address bus is the set of wires that carries
  addresses of memory or I/O only.
• For a memory or I/O to be recognized by the CPU
  it must be assigned an address.
• The assigned address must be unique no two
  devices are allowed to have the same address.
• The CPU puts the address on the address bus, and
  the decoding circuitry finds the device.

11
Computer OrganizationBUS cont.

• b) Data bus
• Data bus is a set of wires that carries data
  only.
• After finding the device through the address bus,
  the CPU uses the data bus either to get data or
  to send data to the device.

12
Computer OrganizationBUS cont.

• c) Control bus
• Control bus is a set of wires that carries
  control signals only.
• The control buses are used to provide read or
  write signals to the device to indicate if the
  CPU is asking or sending information.

13
Computer OrganizationDiagram
CPU
Address bus
RAM
ROM
Disk
Keyboard
Printer/ Monitor
Data bus
Read/Write
Control bus
14
CPU Internal OrganizationDiagram
Address bus
Control bus signals
Data bus
Control Unit
Program Counter Instruction Register REGISTERS
Register A Register B Register C Etc.
Control signals
Data Values
Control signals
ALU
Data values (operands)
Data values (results)
15
MEMORY
16
Memory

• Types of Memory Chips
• ROM
• Read Only Memory, Not able to write to it.
• Non Volatile Retains data when power is
  turned-off
• RAM
• Random Access Memory, able to read and write to
  it.

17
Memory

• Types of ROM Chips
• MROM (Masked Read Only Memory)
• Set by manufacturer and cannot be changed
• Mostly used on consumer appliances where large
  quantities are produced.
• PROM (Programmable Read Only Memory)
• Programmable but only once
• Programmed by blowing internal fuses
• Mostly used for prototypes

18
Memory

• Types of ROM Chips cont.
• EPROM (Erasable Programmable ROM)
• Totally erasable by exposing it to ultra violet
  light for over 20 minutes.
• Programmable outside the circuit.
• EEPROM (Electrically Erasable Programmable ROM)
• Electrically erasable.
• Able to erase a portion of the memory.
• Can be re programmed while in circuit.
• Mostly used for computer BIOS
• FLASH Memory
• Electrically erased, but it erases the entire
  memory.

19
Memory

• Types of RAM Chips
• DRAM (Dynamic Random Access Memory)
• Widely used as main computer memory
• SRAM (Static Random Access Memory)
• Faster than DRAM
• More expensive than DRAM
• Mostly used in Cache memory
• NVRAM (Non Volatile Random Access Memory)
• Does not lose data in memory when turned off.
• Contains an internal Lithium battery to retain
  power

20
Memory Chip Organization

• The internal organization of ROM and RAM chips
  are similar.
• There are two organizations
• Linear Organization
• Two-Dimensional organization

21
Memory Chip Organization

• Linear Organization
• It is a simpler form of organization
• Used if few number of memory locations are needed

22
Memory Chip Internal Linear Organizationof an 8
x 2 ROM chip
01
00
A2
A1
A0
Loc
3 to 8 Decoder
0
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
11
10
1
21
20
A2
2
31
30
A1
3
41
40
A0
4
51
50
5
61
60
6
71
70
E
7
CE
OE
D1
D0
23
Memory Chip Organization

• Two-dimensional Organization
• Used to manage a large number of memory locations
• Allows large memory locations using fewer chips

24
Memory Chip Internal two-dimensional Organization
of an 8 x 2 ROM chip
01
11
00
10
2 to 4 Decoder
0
21
31
20
30
A2
1
41
51
40
50
2
A1
61
71
60
70
3
E
1 to 2 Decoder
0
A0
1
E
CE
OE
D1
D0
25
Instruction Cycle
26
The Instruction Cycle

• The Fetch cycle
• Fetch an instruction from memory, then go to the
  decode cycle
• The Decode cycle
• Decode the instruction determine which
  instruction has been fetched go to execute cycle
  for that instruction.
• The execute cycle
• Execute the instruction, then go to fetch cycle
  and fetch the next instruction.

27
The Instruction Cycle

• The Fetch cycle
• The CPU puts an address of instruction on the
  address bus.
• The memory decodes the address to access the
  desired memory location.
• The CPU allows sufficient time for the memory to
  decode the address and sends a READ control
  signal.
• The READ signal is a signal on the Control bus
  which the CPU sends when its ready to read data
  from memory or I/O device.
• When the READ signal is asserted, the memory puts
  the instruction code to be fetched on to the data
  bus.
• The CPU inputs the data and stores it in one of
  its internal registers.
• The fetch cycle is completed.

28
The Instruction Cycle

• The Decode cycle
• The CPU decodes the instruction.
• Each instruction may require a different sequence
  of operations to execute the instruction.
• The CPU determines which instruction it is in
  order to select the correct sequence of operation
  to perform.
• This is done entirely within the CPU, it does not
  use the system buses.

29
The Instruction Cycle

• The Execute cycle
• The CPU executes the instruction.
• The execution may be
• Read/write data to/from memory.
• Read/Write data to/from an I/O device.
• Perform only operations within the CPU.
• Perform some combination of the above.

30
Sample Diagrams
31
Fetch, Decode Execute Cycles235 operation
32
Fetch, Decode Execute Cycles235 operation
33
Fetch, Decode Execute Cycles235 operation
34
Fetch, Decode Execute Cycles235 operation
35
The End Thanks!!