Advanced FlipFlops CPEG 324 Reading: IBM J' Res' Paper Oklobdzija

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Advanced Flip-FlopsCPEG 324Reading IBM J.
Res. Paper (Oklobdzija)
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Clock signal

• Very important with most sequential circuits
• State variables change state at clock edge.

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Maximum Clock Speed
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Data-to-output (D-Q) delay
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Data-to-output (D-Q) delay
Observation Minimum D-Q delay occurs when CLK-Q
delay is NOT at its minimum value!
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Maximum Clock Speed
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Time Borrowing, Cycle Stealing, Slack Passing
Logic 1 is slower that Logic 2. Do we have to
slow-down the clock to accommodate Logic 1
delay? Or is there a trick here?
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Time Borrowing, Cycle Stealing, Slack Passing

• Lets clock system faster than Logic 1 delay
  permits.
• Because of metastability, CLK-Q delay of CSE2
  will increase.
• If Logic 2 delay is short enough, the increase in
  CLK-Q delay of CSE2 can be absorbed by the 2nd
  stage.

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Engineering Flip-Flops forClock-Skew Absorption
Observation If we design flip-flop circuit to
have flat D-Q curve, then propagation of
clock skew will be reduced! The actual circuit
design is outside the scope of this class.
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Examples of Clock-Skew Absorption
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Lessons Learned

• Maximum clock speed does not occur when CLK-Q
  delay is minimum.
• Slowest stage in a pipeline does not necessarily
  limit the clock speed.
• Flip-flops can be engineered to absorb clock-skew.