Thermal Via Placement in 3D ICs

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Thermal Via Placement in 3D ICs

• Brent Goplen, Sachin Sapatnekar
• Department of Electrical and Computer Engineering
• University of Minnesota

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Overview

• Introduction
• Simplified Example
• Formulation
• Results
• Conclusions

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3D IC Using Wafer Bonding
Generalized view
Detailed view
SOI wafers with bulk substrate removed
Inter-layer bonds
1mm
Bulk wafer
Metal level of wafer 1
10mm
500mm
Device level 1
Adapted from Das et al., ISVLSI, 2003
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Improvements and Obstacles of 3D ICs

• Benefits
• Reduced wirelength
• Lower power per transistor
• Decreased delay
• Higher packing densities
• Smaller chip areas
• Obstacles
• Processing technology
• Thermal issues
• Higher power densities
• Increased thickness
• Insulating materials
• 3D design tools

Joyner, Zarkesh-Ha and Meindl, ASIC/SOC 01
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Methods of Mitigating Thermal Problems
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Thermal Via Regions

• Thermal vias
• Electrically isolated vias
• Used for heat conduction
• Thermal via regions
• Only region where thermal vias are allowed
• Predictable obstacle for routing
• Variable density of thermal vias

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Thermal Vias in 3D ICs
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Benefits and Challenges

• Benefits
• Reduced temperatures
• Uses existing via fabrication
• Benefits 3D ICs more
• Challenges
• Creates obstacles to routing
• Where to put them?
• CAD tools needed

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Overview

• Introduction
• Simplified Example
• Formulation
• Results
• Conclusions

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Simplified Example
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Simplified Example
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Simplified Example
1
2
3
4
5
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10W
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8
9
10
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Simplified Example
10W
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Simplified Example
65oC
70oC
65oC
6oC
6oC
High Temps
10oC/W
10oC/W
59oC
81oC
59oC
10W
10oC/W
10oC/W
27oC
27oC
High temp drop
32oC
36oC
32oC
0oC
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Simplified Example
65oC
70oC
65oC
10oC/W
10oC/W
60
59oC
81oC
59oC
32oC
36oC
32oC
0oC
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Simplified Example
65oC
70oC
65oC
Use thermal gradient not temperature!
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59oC
81oC
59oC
10oC/W
10oC/W
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32oC
36oC
32oC
0oC
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High Temperatures
Place Thermal Vias
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High Thermal Gradients
Place Thermal Vias
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• Impractical to place thermal vias individually
• Use arrangement of thermal vias instead
• Gives thermal via density value
• Changes the effective thermal conductivity

High Thermal Via Density
High Effective Thermal Conductivities
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High Thermal Gradients
High Thermal Via Density
High Thermal Conductivity
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Old Temperatures
Thermal Gradients
Thermal Conductivities
New Temperatures
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Initial Temperatures
Thermal Gradients
Thermal Conductivities
New Temperatures
Thermal Via Densities
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Mathematical Formulation

• Heat transfer within an element (region)
• K ?TP
• Assume P doesnt change between iterations
• Knew ?Tnew Kold ?Told
• Knew Kold (?Told / ?Tnew)
• Using the thermal gradient, g ?T /d,
• Knew Kold (gold / gnew)
• Let gnew slowly approach an ideal value, gideal
• gnew gideal (gold / gideal )a, 0 a 1
• Knew Kold (gold / gideal )1- a
• Update gideal using maximum temperature
• gideal gideal (Tmaxideal / Tmax)

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Thermal Via Placement Algorithm
GIVEN IDEAL MAXIMUM TEMPERATURE Tmaxideal
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Thermal Conductivities of Thermal Via Regions
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Range of Temperature Values

• Midrange thermal via densities produce
• 47.1 lower maximum temperatures
• 28.3 lower average temperatures

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Range of Temperature Values

• Midrange thermal via densities produce
• 47.1 lower maximum temperatures
• 28.3 lower average temperatures

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Results

• Same maximum temperatures as with midrange via
  densities
• 1.8 higher average temperatures
• 11.9 thermal via density in thermal via regions
  (1.2 in chip)
• 50.3 lower than the midrange value

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Results

• Same maximum temperatures as with midrange via
  densities
• 1.8 higher average temperatures
• 11.9 thermal via density in thermal via regions
  (1.2 in chip)
• 50.3 lower than the midrange value

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Before Thermal Via Placement
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After Thermal Via Placement
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Conclusions

• Thermal vias have a greater effect in 3D ICs
• Thermal via regions provide regularity
• Efficient iterative method
• Uses thermal gradients to adjust thermal
  conductivities
• Ideal maximum temperature
• Use lowered value as an objective
• Minimizes use of thermal vias
• Vias are put where they make the most impact
• Reduces thermal resistance on heat conduction
  paths