CSECE 365 COMPUTER ARCHITECTURE

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CS/ECE 365 COMPUTER ARCHITECTURE

• SOUNDARARAJAN EZEKIEL
• Department of Computer Science
• Ohio Northern University

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Three type of instruction

• which includes
• Memory -reference instructions load word (lw)
  and store word(sw)
• Arithmetical-Logical Instruction add, sub, and
  , or, slt
• The instructions branch equal (beq) and jump (j)

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Building data path

• A reasonable way to start a datapath design is to
  examine the major components required to execute
  each class of MIPS instruction
• First Memory Unit
• It is a state element
• hold and supply instructions given an address
• The address of the instruction is kept in a state
  called program counter(PC)

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Two state elements are needed to store and access
instructions
Instruction address
PC
Instruction
Instruction memory
Program Counter
Instruction memory
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Adder

• Lastly, we need adder to increment the PC to the
  address of the next instruction

Add Sum
Adder
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• To execute any instruction,
• fetch the instruction from memory
• to prepare for executing next instruction
• increment the PC so that it points the next
  instruction, 4 bytes later.
• The datapath for step using the above 3 elements
  (memory, pc, adder)

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A portion of datapath used for fetching
instructions and incrementing the PC
Add
PC
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Instruction address
Instruction
Instruction memory
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• Consider R format instructions (Arithmetic
  instruction format)
• they all read two registers, perform ALU
  operation on the content of the registers, and
  write the result
• call this R-type instruction or
  arithmetic-logical instruction(they perform
  arithmetic or logical operations)
• add, sub, slt, and, or
• the processors 32 registers are stored in a
  structure called register file

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Register file

• collection of registers-- any register can be
  read or written by specifying the number of the
  registers in the file.
• It contains register state of the machine
• we need ALU to operate on the values read from
  the registers
• R-formats have 3 registers 2 data word from
  register--- one data word into the register file
  for each instructions

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• write data word --- need 2 inputs one to
  specify the register number--- another is data to
  be written on the register
• write is control by write control signal
• so we need four inputs( 3 for register numbers 1
  for data)
• register number inputs are 5 bits wide (2532)

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The 2 element needed to implement R-format ALU
operations are the register file and ALU
ALU operation
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Reg
5
Read Reg1
Read data1
5
Read Reg2
zero
5
Write Reg
ALU
Data
result
Read data2
data
Write data
RegWrite
Registers
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Note

• the ALU shown above controlled by 3-bit signal
• take 2 32-bit inputs and produce a 32-bit result
• the data path for R-type instructions which uses
  register file, ALU

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The data path for R-type instruction
ALU operation
3
Read Reg1
Read data1
Read Reg2
zero
Write Reg
ALU
Instruction
result
Read data2
data
Write data
RegWrite
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MIPS load and Store

• Consider load word and store word instruction
• general form
• lw t1, offset_value(t2)
• sw t1, offset_value(t2)
• These instructions compute a memory address by
  adding the base register, which is t2, to the
  16-bit signed offset field contained in the
  instruction
• if the instruction is store-- the value to be
  stored must also to be read from the reg file
  where it resides in t1
• it is load-- the value read from memory must be
  written into the reg file in the specified
  register which is t1

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• In addition, we will need to a unit to
  sign-extended the 16 bit offset filed in the
  instruction to 32 bit signed value and a data
  memory unit to read from or write to
• the data memory must be written on store
  instructions, hence it has both read and write
  control signal, an address input as well as the
  an input for the data to be written in to memory

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• the next slide shows how to combine these
  elements to build a datapath for a lw or sw
  instruction
• assumption instruction has been already fetched
• the register number inputs for the register file
  come from the field of instruction

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The 2 units needed to implement loads and stores,
In addition to the register file and ALU
Memwrite
Sign extend
address
32
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Data memory
Write data
MemRead
Sign extension unit
Data Memory Unit
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data path for lw sw, does register access,
followed by a memory address calculation then
read or write from memory, and wirte into
register file if the instruction is a load
Memwrite
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ALU operation
instruction
memwrite
Read reg1
Read data
zero
ALU
Read data 1
address
Read reg2
REG
result
Write data
Data memory
Read data 2
Write data
Write data
Reg write
MemRead
Sign extend
16
32
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beq

• the beq instruction has 3 operands
• 2 registers that are compared for equality
• a-16 bit offset used to compute the branch target
  address relative to the branch instruction
  address
• general for beg t1, t2 , offset
• to implement this, we must compute target address
  by adding sign-extended offset filed of the
  instruction to the PC

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pay attention

• 1. The ISA specifies that the base for the branch
  address calculation is the address of the
  instruction following the branch. Since,we
  compute PC4 ( the address to the next
  instruction)instruction fetch datapath, it is
  easy to use this value as the base for the
  computing the branch target address
• 2. ISA also states that the offset filed is
  shifted left 2 bits so that it is a word offset(
  this shift increase the effective range of the
  offset field by a factor of 4)

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taken

• In addition to computing the branch target
  address, we must also determine whether the next
  instruction is the instruction that follows
  sequentially or the instruction at the branch
  target address.
• When the condition is true (I.e., the operands
  are equal) , the branch target address becomes
  the new PC, and we say that the branch is taken

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not taken

• If the operand are not equal, the incremented PC
  should replace the current PC( just for other
  normal instruction) in this case we say that the
  branch is not taken

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The 2 element needed to implement R-format ALU
operations are the register file and ALU
PC4 from ins datapath
Add
Shift left 2
Branch target
sum
Instruction
Read Reg1
ALU operation
Read data1
Read Reg2
3
Write Reg
ALU
zero
To branch control logic
Read data2
data
Write data
RegWrite
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Sign extend
32
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Plan for next week

• simple implementation scheme
• performance of single cycle machines
• multicycle implementation
• Microprogramming
• Exceptions
• implement datapath in pipelining