Alan Cassell, Jun Li, Quoc Ngo,

1
Nanotechnology in Silicon CMOS Fabrication and
Nanoelectronics
Alan Cassell, Jun Li, Quoc Ngo, Cattien Nguyen,
Bin Yu, and M. Meyyappan NASA Ames Research
Center Moffett Field, CA 94035 email
mmeyyappan_at_mail.arc.nasa.gov
2
Outline
Carbon nanotube interconnects Carbon
nanotubes in chip cooling Carbon nanotube in
microscopy Inorganic nanowire based
nanoelectronics
CNT or other nanomaterial (ex conducting
molecules) based active electronics may be more
than a decade away. In the mean time,
opportunities exist to insert nanomaterials in
silicon CMOS fabrication to address emerging
challenges to continued miniaturization.
3
Nanoelectrode Array (NEA)

• Break a solid micro- or macro electrode into an
  array of 100 to 109 nanoelectrodes
• Each electrode is well separated with the
  neighbors (gt 6R) so that the NEA behaves similar
  to a single NE.
• Can further create an individually addressed
  multiplex array in an array-in-array format

Challenges Reliable fabrication techniques with
affordable cost, particularly for low-density
NEAs.
4
CNT DNA Sensor Using Electrochemical Detection

• MWNT array electrode functionalized with DNA/PNA
  probe as an ultrasensitive sensor for detecting
  the hybridization of target DNA/RNA from the
  sample.
• Signal from redox bases (Guanine) in the excess
  DNA single strands
• The signal can be amplified with metal ion
  mediator oxidation catalyzed by Guanine.

5
Nanoelectrode Array Fabrication
Embedded CNT Array after planarization
30 dies on a 4 Si wafer
6
Electrochemical Detection by AC Voltametry
J. Li, H. T. Ng, A. Cassell, W. Fan, H. Chen, J.
Koehne, J. Han, M. Meyyappan, Nano. Lett., 2003,
3, 597.
7
Cu Damascene Interconnects
G. Steinlesberger, et al., Microelectronic
Engineering, 64, 409 (2002).
H. H. Hwang, M. Meyyappan, G.S.Mathad, and
R.Ranade, J. Vac. Sci. Technol., B 20(6), 2199
(2002).

• Challenges
• Etching high aspect ratio features
• Void-free filling
• Surface and grain boundary scattering
• Electromigration

Chen et al., IEEE Elec. Dev. Lett., 19, 508(1998)
8
Carbon Nanotube Interconnects ?

• CNT advantages
• Small diameter, high aspect ratio
• High current carrying capacity
• Highly conductive along the axis
• High mechanical strength

Infineon
Question How to integrate this into
device processing?
9
Process Flow for PECVD-Grown CNFs
As-grown CNF array

• CNFs, with their vertical orientation, have
  the capability to fulfill both size and
  performance requirements for next generation ICs
• In contrast, SWNTs in spite of their better
  conductivity are not ideal since filling a via
  with spaghetti-like structures is not useful.

STEM showing CNF morphology
CNF array embedded in SiO2
Li et al., Appl. Phys. Lett, 82, 2491 (2003)
10
I-V Characteristics of a Pd-Catalyzed CNF
Parallel nature of CNF walls is better for
current transport.
11
Reliability Measurement of CNF Via
No degradation of CNF via was observed over
several days of high current density stress
12
21 nm diameter, 4 ?m tall via
Copper vs CNF via

• Measurement (Pd-catalyzed CNF)
• 50 ??-cm
• R 5.8 k?

Theoretical Estimate

• 2.7 ??-cm
• R 312 ?

Practical measurements, when done, likely to
resistance
Opportunities exist to improve and resistance
13
Nanotube Materials for Hubble Space Telescope
(HST)
Current Problem Hubble Space Telescope Imaging
Spectrograph overheats, causing data
degration Solution Carbon Nanotube (CNT) as
thermal interface greatly improves HSTs ability
to dissipate excess heat This technology has
been licensed to industry for computer chip
cooling.
PI Alan Cassell Team Members Jun Li, Brett
Cruden, and Quoc Ngo
14
Carbon Nanotubes for Chip Cooling
Material MWNTs intercalated with Cu
(electrochemical approach)
15
Comparison to Real Thermal Budget
Normalizing to Area
RCNT/Cu0.404 K/W
Sample 1
RCNT/Cu0.358 K/W
Sample 2
Sample 3
RCNT0.42 K/W
R. Viswanath et. Al, Intel Tech. Jour., Q3 (2000)
Best recent result RCNT/Cu 0.098 cm2.K/W
16
Mechanical Stability of CNT/Cu Film
Before compressive stress
After compressive stress
Fiber integrity is maintained up to 60 psi
(normal pressure values for packaging)
17
CNT in Microscopy
Atomic Force Microscopy is a powerful technique
for imaging also CD metrology, nanomanipulation,
as platform for sensor work, nanolithography... C
onventional silicon and other tips wear out
quickly. CNT tip is robust, offers amazing
resolution.
2 nm thick Au on Mica imaged with SWNT
Simulated Mars dust
Written using multiwall tube
Nguyen et al., Nanotechnology, 12, 363 (2001)
18
MWNT Scanning Probe
Profilometry in Semiconductor Manufacturing
19
Nanowire as Nano-Chip Component

• One-Dimensionality
• Lowest-dimension transport channel for best FET
  scalability
• Lithography-less Approach
• Vertical transistor does not depend on
  lithography for defining source-drain separation.
• Unique Physics
• Reduced phonon scattering (logic)
• Surface sensitivity to external excitation
  (memory)
• Quantum confinement (logic/memory)
• Bandgap inversely proportional to the radius
• Variety of Material Choice
• Semiconductor, metal, superconductor, IV, II-VI,
  III-V,
• High Level of Integration
• Device / interconnect co-design ultra-compact
  chip design (e.g., SRAM, NVM, FPGA)

20
Experimental Setup Growth Methodology
21
Vertically-Aligned Nanowires for Device
Fabrication
z
Germanium Nanowires
P. Nguyen et al., Advanced Materials, Vol. 17, p.
549 (2005).
22
Vertical Surround-Gate Field Effect Transistor
A schematic illustrating the device architecture
of a VSG-FET.
A process flow outlining the major fabrication
steps of a VSG-FET.
Ng et al., Nano Letters, Vol. 4 (7), p. 1247
(2004)
23
Vertical Surround-Gate Field Effect Transistor
Ng et al., Nano Letters, Vol. 4 (7), p. 1247
(2004)
24
Nanowire FET-On-Insulator
1-D nanowire Self-assembly

• Direct integration of large array of nanowire FETs

Metal (e.g., Ti/Au)
c)
a)
Si (100) substrate
PMMA
d)
b)
25
Ge-NOI Field-Effect Transistor Electrical
Characteristics

• Both N- and P-channel nanowire FETs
• Lg13µm
• tox600A
• The performance should be further improved by
• Scaling down device critical dimensions (Lg, tox)
• Removing Schottky barrier
• Minimizing surface scattering by passivation

26
Nanowire FET Logic Functionality

• On-off ratio increases after thermal anneal
• Ion/Ioff 105 logic switch operation is achieve
• S/D-channel Schottky barrier reduction
• Metal diffusion/alloy formation

27
Summary
Entirely CNT-based or molecule-based
electronics may be far term prospects In the
mean time, it is possible to get benefits from
nanotechnology to solve near and mid-term
problems in silicon CMOS fabrication. Some
examples include - Interconnects - Thermal
interface materials - Profilometery and
Metrology - Novel device architectures