Space Qualification of Hardened by Design ASICs

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Space Qualification of Hardened by Design ASICs

• MRQ Workshop
• December 11, 2001
• Presented By
• David R. Alexander
• Mission Research Corporation Microelectronics
  Division
• 5001 Indian School Road, NE, Albuquerque, New
  Mexico 87110
• Phone [phone] E-mail
  dralexa_at_mrcmicroe.com dralexa_at_mrcmicro.com

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Topics for Discussion

• HBD History
• Capabilities of HBD Cell Libraries
• Limitations of HBD Cell Libraries
• Potential of HBD Cell Libraries
• Issues in the Development of HBD Cell Libraries
• Comments on Qualification of Small Quantity HBD
  Microcircuits

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HBD Projects

• Project Status Sponsor
• Concept Demo 1.2µ, 0.8µ, 0.5µ Complete AFRL/Phil
  lips
• HBD Analog Design at 0.8µ Complete AFRL/Phillip
  s
• Port Expander Design at 0.5µ Complete AFRL/Phil
  lips
• Concept Demo 0.35µ Complete Intersil
• ASIC Development at 0.35µ On-going SNL
• NSC Gate Array Test Chip 0.35 Complete NSC/AFRL/
  Phillips
• Concept Demo 0.25 SOI Complete AFRL/Phillips
• FFT ASIC at 0.25 SOI On-going AFRL/Phillips
• Commercial Macro Insertion in HBD On-going AFRL/
  Phillips
• ROM Compiler Development On-going Boeing/DTRA
• HBD 10 bit ADC On-going DTRA
• Temporal Latch Development On-going DTRA
• Advanced HBD Library 0.18µ On-going DTRA
• HBD for Dose Rate 0.25µ On-going NSWC/Crane
• Rad Hard WSSP On-going AFRL/Rome

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Total Ionizing Dose Induced Edge Leakage
MRC Microelectronics A Division of
Mission Research Corporation
5
Total Ionizing Dose Induced FOX Leakage
MRC Microelectronics A Division of
Mission Research Corporation
6
Single Event Latchup
MRC Microelectronics A Division of
Mission Research Corporation
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Primitive Cell in Hardened by Design Gate Array
Vdd Contacts
Vss Contacts
P-plus Source/Drain
Scaled PMOS
Annular NMOS
N-Plus Source/Drain
MRC Microelectronics A Division of
Mission Research Corporation
8
Transistor Characteristics
HBD Test Chip for TSMC 0.35 Micron

• Standard test chip for radiation testing
• Processing cost lt 10K

MRC Microelectronics A Division of
Mission Research Corporation
9
Available Library Cells

• 205 Total Cells Available
• Combinational
• 4 AND /12 AOI / 12 BUF / 12 HIZ-INV / 6 BUF / 3
  CLK-GEN / 6 INV/ 3 MAJ / MUX / 4 NAND / 3 NOR / 6
  OAI / 3 OR / PULLUP / PULLDWN / XNOR / XOR / 6
  ZBUF / 6 ZINV
• Sequential
• 21 TLAT / 7 D-LAT / 14 DICE-DLAT / 18 FLIPFLOP /
  7 DICE-FLIP-FLOP / 18 BUF-LAT
• 28 Types of I/O Pads (Tandem Staggered)
• Foundries
• TSMC 0.35 0.25
• UTMC/AMI 0.50
• HP 0.5 0.35
• NSC 0.35 0.25
• Peregrine 0.5

MRC Microelectronics A Division of
Mission Research Corporation
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Library Cells for Single Event Hardening

• Hardened by design cells available for SEU/SET
  mitigation
• DICE latch cells use a cascode design
• Calin, T. et al., IEEE Trans. Nuc. Sci, 43, 2874
  (1996)
• Two nodes must be struck simultaneously to
  generate an upset
• Temporal latches use TMR and a 4 phase clock to
  eliminate SEU and SET effects.
• www.mrcmicroe.com

DICE Latch
Temporal Latch
MRC Microelectronics A Division of
Mission Research Corporation
11
HBD Gate Array Selection
MRC Microelectronics A Division of
Mission Research Corporation
12
HBD ASIC Design Flow
MRC Microelectronics A Division of
Mission Research Corporation
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Hardened By Design Gate Array Application

• 60K gate array HBD ASIC
• 140 I/O
• Fabricated using TSMC 0.35 micron 5.0 volt
  process
• DICE latches for SEU hardening

Data courtesy of Sandia National Labs
MRC Microelectronics A Division of
Mission Research Corporation
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Heavy Ion Test Results for HBD ASIC
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Limitations of HBD Cell Libraries

• HBD at MRC means no changes in process and no
  violation of foundry design rules
• HBD trades performance, area, and density for
  radiation hardness
• Area penalty is a factor of 3.2x to 1.6x
• Performance penalty is 50 to 10
• Designs are often pad limited
• Cell library is currently limited to basic cells
  with a limited variety of drive strengths.
  Complete capability requires
• Greater variety of basic cells and drive
  strengths
• Memory compilers
• Data path compilers
• Library cells for mixed signal design
• Scan cells with support of scan insertion tools
  and ATPG
• Temporal latch insertion software (in
  development)
• Dose rate hardening methodology (in development)
• I/O variety (LVDS in development)
• Access to advanced place and route tools

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Potential for HBD

• Dependent on access to foundries
• Dependent on definition of qualification
  procedures
• Does not fit in either QPL or QML category
• Requires acceptance by system integrators and
  SPOs
• Dependent on a viable business model
• Library sales
• ASICs
• Standard products
• Technology is viable assuming no new failure
  mechanisms at smaller feature sizes

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Issues in the Development of HBD Cell Libraries

• Cost and access to EDA tools
• E-ECAD Business Model
• PC based vs Work Station based
• Pricing of EDA for design centers
• Access to foundries
• Expanded MOSIS service
• On-shore vs Off-shore
• Qualification

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QML Flow

• Quality cannot be tested in
• Quality must be designed and fabricated in
• Quality in semiconductors is best achieved in
  high volume foundries under statistical process
  control with no changes in a production process

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HBD ASIC ACQUISITION

• Mil-Prf-38535 Permits a Radiation Hadened Source
  of Supply to Manage the QML Flow
• Acquisition Model
• Conversion of Customer Requirements Design
  Center
• RTL Level Design/Test Bench/Timing Simulation --
  Customer
• Synthesis/Place Route/Back Annotation/Checking
  Design Center
• Fabrication to wafer acceptance parameters
  Commercial Foundry (MOSIS)
• Technology Quality Conformance Inspection
  Failure Analysis Vendor (Analytical
  Solutions/Solecon)
• Package Selection/Design Customer / Design
  Center
• Custom Package Fabrication Packaging Vendor
  (Kyocera)
• Package Qualification Part Assembly QML
  Assembly Vendor (Pantronix)
• Electrical Testing/Burn-in/Life Testing
  Customer/Design Center
• Documentation Control Parts Testing
  Customer/Design Center

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Cost Analysis for 25 HBD Space Flight Parts
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Summary

• Hardened by Design techniques can provide a cost
  effective route to obtain small quantity,
  radiation hardened ASICs
• Reduced feature size permits ASICs of significant
  complexity to be fabricated with HBD techniques
• HBD cell libraries are gaining maturity to
  support synthesized ASIC designs
• Qualification can be managed economically in a
  HBD approach

MRC Microelectronics A Division of
Mission Research Corporation