Module 9 : VHDL-based Synthesis

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Module 9 VHDL-based Synthesis
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Goal

• This module presents the basic concept of
  VHDL-based Synthesis
• The first lecture presents several description
  styles
• The second lecture presents many examples of VHDL
  descriptions at various abstraction levels and
  description domains
• VHDL files related to the solution of exercises
  proposed in Modules 6 and 7 are available to be
  downloaded.

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Prerequisites

• Students have to be familiar with the basic
  concepts of VHDL language (see Module 8).

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Structure

• This module includes the following 6 lectures
• 9.1 VHDL description styles
• 9.2 Some examples

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Examples Exercises

• The complete solutions of some Exercises and
  Examples proposed within the Lectures are
  available

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VHDL files

• The VHDL files (.vhd) related to several
  exercises and examples solved within the lectures
  are available.
• They are zipped in 2 files, related to Exercises
  and to Examples proposed within the Lectures,
  respectively.

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