Lecture

1
Lecture 0 Introduction
ECE 410 VLSI Design
2
Integrated Circuits (ICs)
Chip
Wafer
Chip Layout with bonding Pads
Photo for fabricated Chip

• Scale of Integration
• SSI (Small-Scale Integration)
• MSI (Medium-Scale Integration)
• LSI (Large-Scale Integration)
• VLSI (Very-Large-Scale Integration)
• ULSI (Ultra-Large-Scale Integration)
• WSI (Wafer-Scale Integration)

• Technologies
• MOS (Metal-Oxide-Semiconductor)
• BJT (Bipolar Junction Transistor)
• GaAs (Gallium Arsenide)
• BiMOS (Bipolar-MOS)

3
Integrated Circuits (ICs)

• Scale of Integration
• In practice, many gates are manufactured on a
  single IC chip. Although there are no universally
  accepted definitions for level complexity, we
  define the level of complexity as follows
• SSI (Small-Scale Integration) 1-10 gates on
  a chip
• Simple gates, flip-flops, decoders,
  multiplexers, etc.
• MSI (Medium-Scale Integration) 10-100 gates on
  a chip
• Counters, shift-registers, 4-bit adders, etc.
• LSI (Large-Scale Integration) 100-1000 gates
  on a chip
• ALUs, simple microprocessors, higher-bit
  adders, etc.
• VLSI (Very-Large-Scale Integration) 1000-10000
  gates on a chip
• ALUs, 8-bit microprocessors, microcomputers,
  Digital signal processors, etc.
• ULSI (Ultra-Large Scale Integration) above 10000
  gates on a chip
• WSI (Wafer-Scale Integration)

4
Semiconductor Manufacturing Process
5
Semiconductor Manufacturing Process
6
Semiconductor Manufacturing Process
7
Semiconductor Manufacturing Process
8
Semiconductor Manufacturing Process
9
Semiconductor Manufacturing Process
10
Semiconductor Manufacturing Process
11
IC Packages
SOIC
TSOP
DIP
PGA
Pin Grid Array
Small Outline IC
Thin Small outline Package
Dual Inline Package
SOJ
PLCC
PQFP
BGA
Plastic Quad Flat Package
Plastic Leadless Chip Carrier
Small outline J-Leaded Package
Ball Grid Array
12
IC Packages
DIP
DIP (Dual Inline Package) - The most popular
first generation IC package type. - Many DIP
devices translate directly to SOIC or TSOP
packages for higher density applications.

• PGA (Pin Grid Array)
• - Second generation package. 
• Still thru-hole, but the package size is reduced
  by moving pins to the underside of the packages
  in a grid pattern.
• - The grids are called out by the pins in the x
  direction and the y direction.

PGA
SOIC

• SOIC (Small Outline IC)
• - The first surface-mount package to replace
  small pin count (8-16) DIP. 
• Also called "Gull Wing" packages, referring to
  the shape of their pins.
• - Very popular for higher pin count (up to 64
  pins), mostly memory types of ICs.

TSOP

• TSOP (Thin Small Outline Package)
• - A special variation of the SOIC. "T" means a
  thin package
• The TSOP I has the pins on the WIDE edge. 
• The TSOP II has leads on NARROW side and looks
  more like a DIP package that was shrunk and
  turned into a surface mount package.

13
IC Packages
SOJ

• SOJ (Small Outline J-Leaded) package
• A surface-mount equivalent to a thru-hole DIP. 
• Pins protrude on two sides of the plastic package
  body and curl under it. 
• The lead looks like the letter "J", so referred
  to as a J-leaded package.

PLCC

• PLCC (Plastic Leadless Chip Carrier
• Third generation packaging. 
• A more popular version of the SOJ.  
• Has leads on all four sides.

• QFP or PQFP (Plastic Quad Flat Pack)
• QFPs are high-density, surface-mount packages
  with leads protruding on all four sides of the
  package. 
• The QFP has the most variations of any package
  type and must be carefully specified for adapters.

PQFP
BGA

• BGA (Ball Grid Array)
• One of the latest in high-density, surface-mount
  packages. 
• The package is similar to PGA. 
• Pin connections are solder balls in a grid
  pattern, in the package bottom.

14
IC Design Levels of Design Abstraction
Description of circuits in large blocks and
estimates of chip area (Behavior Area estimate)
Architectural Level
Partitioning of blocks into smaller functional
modules (Functions Timing)
Register Transfer Level
Description of blocs as logic gate and sequential
elements (Bits Timing)
Logic Level
Description of elements as a transistor and
parasitic elements (Voltages Currents)
Circuit Level
Description of elements as a transistor and
parasitic elements (Voltages Currents)
Physical Level
Device Level

• Device modeling and electrical char. of
  transistors (I/V Char.)

Technology Level
Characterization of impurity profiles (Impurity
Profiles)
15
IC Design IC Applications

• Two distinct classifications for ICs are as
• Standard Parts Components used by many system
  manufactures.
• Custom Parts
• Full-Custom Circuits
• Components designed and manufactured for one
  custom.
• Semi-Custom Circuits
• Some standardize patterns or masking layers are
  pre-processed on the chip.
• Custom parts are used when suitable standard
  parts are not available, or to reduce cost by
  providing exactly the function needed for a
  specific application.