BTeV Software Tools Status Report

1
BTeV Software ToolsStatus Report

• Ted Bapty
• Sandeep Neema
• Vanderbilt Univ.

2
Outline

• ISIS tasks
• Status Overview
• Fault Mitigation Modeling
• Fault Mitigation Code Generation
• Fault Mitigation Runtime Interfaces
• Code optimization preliminary results

3
VU/ISIS BTeV Responsibilities

• Tools for System Design Integration
• Modeling Tool
• Runtime (Integration Platform?) Synthesis
• Methods for Dynamic Fault Recovery
• Fault Recovery Modeling
• Fault Mitigation Controller Synthesis/Configuratio
  n
• Tools for Analysis
• Prediction of System Characteristics
• Verification of Fault Behavior
• Testbed
• Based on existing hardware, TMS320C6711 Modular
  Arch.
• Flexible experimentation platform

4
Status

• Modeling Environment Revisions
• Fault mitigation modeling
• Generation
• Generating mitigation engines (preliminary)
• Trigger Code
• First pass at optimization, 6-10x speedup on some
  modules.
• Hardware Parts procured, PCB in fab, expect
  hardware in 1 month.

5
Fault Mitigation Modeling
6
Fault Mitigation Modeling

• Captures logical information flow between Fault
  Managers
• Architecture diagram to capture fault mitigation
  hierarchy
• Captures fault mitigation behavior as finite
  state machines
• States model failure states of the node/network
• Transitions are triggered by faults or mitigation
  commands
• Transition actions capture failure mitigation
  instructions
• TBD action language / fault mitigation API

Demo
7
Fault Mitigation Code Generation

• Generate C-code modules from Fault-mitigation
  (state machine) models
• Unknowns/Assumptions
• Fault Mitigation Task
• How often is it executed?
• How are faults/fault mitigation commands
  propagated to this task?
• Mailboxes, semaphores,
• Message format of the fault mitigation
  command/response
• Fault Mitigation API

Demo
8
Fault Mitigation Interface

• Fault Mitigation Interface
• The FMA interfaces with the local diagnostics
  facility (receive local status, clear errors,
  trigger rediagnosis, set diagnosis mode, etc.
• Commands
• RETRY_LINK(link_id)
• Function Reset/resync a comm link,
• Returns failure or success
• REROUTE_LINK(link_id)
• Function Reroute communications through a
  separate link
• ADD_TASK(task_id, link_id)
• Function Adds a task to the task list, operate
  on data from link_id
• TEST_MEMORY(memory_bank)
• Function Intensive test on memory bank
• RELOCATE_DATA(from_bank, to_bank)
• Function Moves data, marks source memory bank as
  unused/unavail
• GET_LOCAL_STATUS
• Function Reports status of a resource on a
  local node
• SEND_MESSAGE
• RECEIVE_MESSAGE
• . . .

9
Code OptimizationGuidelines

• The compiler tools for CCS 2.0 include an
  optimization program that improves the execution
  speed by performing tasks such as simplifying
  loops, software pipelining, rearranging
  statements and expressions, and allocating
  variables into registers.
• Standard Looping Constructs are Preferred
• Goto statements, though sometimes necessary,
  should be used with extreme caution
• Compiler may suppresses certain optimizations
  trying to handle goto statements (software
  pipelining, trip counters, function inlining)
• Structured and easily-readable control flow is
  maintained

10
int function() int donepos 0 int
i0 int done 0 while(!done)
for( i0ilt10i) if
(condition_A) cout ltlt
"if" ltlt endl if (donepos
0) cout ltlt "do positive tracks" ltlt
endl donepos 1 break
else return 0
else
cout ltlt "else" ltlt endl if
(donepos 0) cout ltlt "do
positive tracks" ltlt endl donepos 1 break
else
return 0
return 0

• Int function()
• int donepos 0
• int i0
• int done 0
• goto start
• dopos
• cout ltlt do positive tracks" ltlt endl
• donepos 1
• start
• while(!done)
• for( i0ilt10i)
• if (condition)
• cout ltlt "if" ltlt endl
• goto nexti
• else
• cout ltlt "else" ltlt endl
• goto nexti

Convert to standard loop constructs
Rearranged function exhibits 9x speed
improvement over previous function
11
Higher Parallelism
Indicates parallel execution
12
CCS 2.0 Optimization

• Rearranged function exhibits 9x speed
  improvement over previous function
• Simple C/ASM
• Compiler/Optimizer works best with simplistic
  code
• Scheduled or chip-specific ASM should be avoided
  if using the optimizer

13
Synthesis Analysis/Offline

• Simulation
• Functional (e.g. Matlab)
• Performance (Timing, Discrete Event)
• Interfacing/generating to Swarms/Jackal/TAEMS
• Diagnosability
• Failure Modes Sensors
• Predict ability to Detect/Isolate Failures
• Reliability Analysis
• Predict MTBF, Maximum Failures
• Robustness
• Stability Analysis
• Reconfiguration Strategies/Control System

14
Extra Slides
15
Analysis
Modeling
System Models
Reconfig Behavior
Resource
Performance Simulation
Diagnosability Analysis
Synthesis
Design and Analysis
Reliability Analysis
Feedback
Algorithm
Fault Behavior
Synthesis
Runtime
Region Operations Mgr
Experiment Interface
Global Operations Manager
Region Fault Mgr
Local Oper. Manager
L1/ DSP
Local Oper Manager
L2,3/ RISC
Logical Control Network
Logical Control Network
Local Fault Mgr
Logical Control Network
Local Fault Mgr
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
ARMOR/RTOS
ARMOR/Linux
Global Fault Manager
Logical Data Net
Logical Data Net
Local Oper. Manager
Local Oper Manager
DSP
RISC
Local Fault Mgr
Local Fault Mgr
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
Trig Algo.
ARMOR/RTOS
ARMOR/Linux
Soft Real-Time
Hard
16
System Modeling
17
Modeling Language (Preliminary)
Processing Data Flow
Hardware Resources
Hierarchical Fault Management
Full
Recov. Mode 1
Recov Mode 3
Recov. Mode 2
Concepts Processes, streams, data channels,
Functions, data types, communication
Concepts Processors, Memory, Topology,
Reliability, Failure Modes,
Concepts Recovery Strategies, Modes of
Operation, goals/importance
18
Mitigation Messages

• SEND_MITIGATION_ACTION_TO_CHILD
• REPORT_MITIGATION_FAILURE_TO_PARENT
• LOCAL_STATUS_CHANGE from local diagnostics
• MITIGATION_CHILD_REQUEST from children of the
  mitigation agent