Smart Dust Mote Core Architecture

1
Smart Dust Mote Core Architecture

• Brett Warneke, Sunil Bhave
• CS252
• Spring 2000

2
Smart Dust Overview

• Autonomous sensing and communications in 1 mm3
• Multiple sensors temperature, light, vibration,
  etc.
• Batteries 1 J/mm3
• Downlinkbroadcast only
• Uplink CCR draws 6.4pJ/bit

3
System Diagram

• Core
• Transceiver back end
• Sensor Signal Processing
• Computation
• Memory

Sensors
Power Supply
ADC
Receiver Front End
CCR Driver
Real Time Clock
4
Design Goals

• Minimize energy through architecture
• Minimum energy Þ ASIC implementation
• Dynamic reconfigurability
• How much is necessary tradeoff with ASIC
  mapping
• Energy driven operation modes
• Military base monitoring
• Typical application scenario to guide design
• Detect heat and vibration of vehicles
• Real time sensor readings
• Logged sensor readings

ASIC
Microprocessor
5
Desired Operations

• Immediate
• Transmit ID ? Mote health report
• Transmit current readings from one/all sensors
• Send logged data for sensor X
• Calibrate real-time clock
• Reconfiguration
• Start logging data from sensor X sampled every T
  seconds
• Set logging threshold and filter coefficients
• Set ScatterCast interval to T seconds
• Set your wakeup interval to T seconds

6
One Approach Golden Processor
7
Golden Processor Features

• Laser Reprogrammable
• Gated clocks everywhere
• Processor stall mode
• Eight execution phases
• 1 cpi including fetch
• No pipelining to reduce overhead
• Forced sequencing
• Minimize glitching
• Prevent bus conflicts and thus short circuit
  current
• Robust to delay variations from process spreads,
  voltage swings (will test from 0.3V to 1.4V), and
  temperature

8
New Approach Top-Level Diagram
Sensors
Setup Memroy
Timer Bank
Power Supply
ADC
Receiver Front End
Reconfigurable Datapath Components
CCR Driver
Real Time Clock
SRAM
9
Timers and Setup Memory

• All activity initiated by timers
• When timer expires, Setup Memory 1 configures the
  datapath
• Additional setup memories can be invoked to
  perform more steps
• Two rates available for each timer
• Two sensor sampling rates for normal polling and
  interesting events
• Delay receiver for a long period before returning
  to normal rate
• Multiple setup memory banks for energy-driven
  operation modes

10
Reconfigurable Datapath Components
Immediate Mode Setup Reg
Global Setup Reg
Threshold Mem n

• Immediate mode packets load Immediate Mode Setup
  Register to configure the datapath
• Data-driven components
• Wiring options
• many point-to-point control and data wires
• wire mesh with switches for routing

11
Example Configuration Sensor Logging
Timer value 1
Timer value 2
Setup Mem 1
Timer
Setup Mem 2
5
4
3
2
1
0
Zero
Open control signals are driven by the setup
memory
Done
PWR
PWR
PWR
Sensor
ADC
Done
PWR
Data
Adder
False
Done
Data
WE
SRAM
Comparator
True
PWR
Data
PWR
Addr
Sensor Reg
Threshold Mem
PWR
Data Addr Reg
12
Comparison of Three Architectures

• ARM8 estimations from Peggy Laramie, M.S. thesis
  1998
• energy is for a set of instructions equivalent to
  the configuration on the previous slide
• Vdd1V (scaled from the reported numbers)
• Energy estimations for other approaches were to
  be from Powermill

13
Conclusions

• Smart Dust needs minimum energy controller
• New non-microprocessor architecture designed
• Timer controlled
• Reconfigurable datapath
• Should be much lower energy than a microprocessor
  architecture, but unconfirmed