The NA60 Experiment Readout Architecture

1
The NA60 Experiment Readout Architecture

• M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky,
  H.Ohnishi for the NA60 Collaboration

13th IEEE- NPSS Real Time Conference 2003, Hotel
Omni Mont Royal, Montreal, Canada, May 18 23
2003
2
The NA60 Experiment

• Fixed target experiment at CERN SPS
• Heavy Ion / Dimuon experiment
• Open charm and prompt dimuon production
• Talk Outline
• Apparatus
• DAQ Architecture
• Readout Electronics
• Conclusions

3
Detector Concept and Layout

• 4 Detectors
• Muon Spectrometer (MWPCs, Trigger hodoscopes)
• ZDC
• Beam Tracker
• Vertex Detector

4
DAQ Overview
Detector
Detector
Detector
LDC
DATE ALICE
System is organized in indipendent partitions
GDC
Castor/ CDR
5
PCI System

• Many partitions
• A General-purpose PCI card
• Many detector-specific mezzanines

6
Readout Chain Overview
BURST
Acquisition software (DATE)
7
Hardware/Software Handshake
10
10
10
11
11
11
BURST
At the end of the burst HW sets bit 2
bits 0-1 SPS status bit 2 R/O status bit3
timeout
00 idle 10 burst 11 interburst
timeout
SW starts as soon as bit 2 is set and resets it
at the end
If a new burst arrives while SW is still reading
bit 3 is set
Acquisition Software
8
PCI Card Architecture
PCI interface
RAM
CTRL
PCI
INTERBURST
application
mez.
Registers
det.
Control logic
BURST
PCI Card
Light blue blocks inside FPGA

• FPGA
• Large memory buffer

• Mezzanine Cards
• Registers

9
First Implementation PCI-FLIC

• Developed by EP/ED-DTb CERN Division
• PCI core embedded in ORCA FPGA
• Successfully used in test beams in 2001/2002
• Readout architecture validated
• Has some limitations
• Slow FPGA
• Maintenance problems
• A new card has been developed...

10
Final Implementation PCI-CFD

• New and faster ALTERA FPGA
• External PCI bridge (PLX 9030)
• X4 bandwidth

64 MBytes RAM
FPGA (APEX/ 20K100)
PMC connectors for mezzanine cards
PLX9030 PCI bridge
11
CFD FPGA Application
Readout
Event Formatting
BURST
RAM Writing
INTER BURST
PCI Interface
12
Mezzanine 1 VME-Like CAMAC Protocols

• Very simple mezzanine
• Level conversion ECL/NIM gt TTL
• Protocol itself implemented in PCI Card FPGA

BUSY
BURST WARNING TRIGGER
PCI Card
Protocol control signals data
13
Mezzanine 1 Protocols

• 2 different protocols implemented on this
  mezzanine
• RMH Protocol (Muon Spectrometer MWPCs
  Hodoscopes)
• Fera (CAMAC) protocol (Beam Tracker ZDC)

RMH Protocol
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Mezzanine 2 - Pixel Detector
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Mezzanine 2 Mezzanine Features

• Complex mezzanine
• Can be interfaced to 2 pixel planes
• R/O implemented in local FPGA
• Zero Suppression
• Event formatting
• Error detection
• PCI accesses FIFOs
• Detector configuration

16
Mezzanine 2 Pixel ConfTest Software

• Mezzanine pixel-chip configuration (JTAG)
• Settings database
• Detector R/O Chip test
• Threshold scan
• Noisy and dead pixel
• Used by DATE at run startup

17
Conclusions

• A new readout system based on the PCI bus has
  been developed for a HEP experiment
• High performances and flexibility, low costs
• Roadmap
• Muon spectrometer electronics commissioned
  October 2001
• Beam Tracker and ZDC electronics used for the
  first time June 2002
• Pixel Telescope intermediate system working on
  beam June October 2002
• Final system working in lab, will be used in data
  taking August 2003

18
Acknowledgements

• The authors would like to thank the following
  people
• CERN EP/ED-DTb group and in particular Hans
  Muller for their contributions and suggestions in
  the early stages of the project
• The Alice Pixel group and in particular
  F.Formenti, G.Stefanini, K.Wyllie, A.Kluge and
  M.Burns for their constant support to the NA60
  pixel project

19
NA60 Collaboration
R. Arnaldi, K. Banicz, K. Borer, J. Buytaert,
J. Castor, B. Chaurand, W. Chen,
B. Cheynis,C. Cicalò, A. Colla, P. Cortese, A.
David, A. de Falco, N. de Marco, A. Devaux, A.
Devismes,A. Drees, L. Ducroux, H. Enyo, A.
Ferretti, M. Floris, P. Force, A. Grigorian,
J.Y. Grossiord,N. Guettet, A. Guichard,
H. Gulkanian, J. Heuser, M. Keil, L. Kluberg, Z.
Li, C. Lourenço,J. Lozano, F. Manso, A. Masoni,
A. Neves, H. Ohnishi, C. Oppedisano, G. Puddu,
E. Radermacher, P. Rosinský, E. Scomparin,
J. Seixas, S. Serci, R. Shahoyan, E. Siddi,
P. Sonderegger, G. Usai, H. Vardanyan and H. Wöhri
50 people, 12 institutes, 7 countries