Interface technieken Van SOC naar AMBA

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Interface technieken Van SOC naar AMBA

• J.F. van der Bent

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De Systeembus

• Welke onderdelen bevat een systeembus?
• De databus
• De adresbus
• De besturingsbus

Controle bus
CPU
I/O
Mem
adresbus
databus
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Introduction

• Technological Advances
• todays chip can contains 100M transistors .
• transistor gate lengths are now in term of nano
  meters .
• approximately every 18 months the number of
  transistors on a chip doubles Moores law .
• The Consequences
• components connected on a Printed Circuit Board
  can now be integrated onto single chip .
• hence the development of System-On-Chip design .

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What is SoC ?

• People A
• The VLSI manufacturing technology advances has
  made possible to put millions of transistors on a
  single die. It enables designers to put
  systems-on-a-chip that move everything from the
  board onto the chip eventually.
• People B
• SoC is a high performance microprocessor,
  since we can program and give instruction to the
  uP to do whatever you want to do.
• People C
• SoC is the efforts to integrate heterogeneous
  or different types of silicon IPs on to the same
  chip, like memory, uP, random logics, and analog
  circuitry.
• All of the above are partially right, but not
  very accurate!!!

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What is SoC ?
SoC not only chip, but more on system. SoC
Chip Software Integration The SoC chip
includes Embedded processor ASIC
Logics and analog circuitry Embedded
memory The SoC Software includes OS,
compiler, simulator, firmware, driver, protocol
stackIntegrated development environment
(debugger, linker, ICE)Application interface
(C/C, assembly) The SoC Integration includes
The whole system solution Manufacture
consultant Technical Supporting
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System on Chip architecture
ASIC Typical Design Steps

• Typical ASIC design can take up to two years to
  complete

Top Level Design
Unit Block Design
Unit Block Verification
Integration and Synthesis
Trial Netlists
Timing Convergence Verification
System Level Verification
Fabrication
DVT Prep
DVT
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12
12
4
8
14 ??
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Time in Weeks
48
Time to Mask order
61
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System on Chip architecture

• With increasing Complexity of ICs and
  decreasing Geometry, IC Vendor steps of
  Placement, Layout and Fabrication are unlikely to
  be greatly reduced
• In fact there is a greater risk that Timing
  Convergence steps will involve more iteration.
• Need to reduce time before Vendor Steps.
• Need to consider Layout issues up-front.

SoC Typical Design Steps
Top Level Design
Unit Block Design
Unit Block Verification
Integration and Synthesis
Trial Netlists
Timing Convergence Verification
System Level Verification
Fabrication
DVT Prep
DVT
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4
4
2
14
5
Time in Weeks
24
Time to Mask order
33
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System on Chip interconnection

• Design reuse is facilitated if standard
  internal connection buses are used .
• All cores connect to the bus via a standard
  interface .
• Any-to-any connections easy but
• Not all connections are necessary .
• Global clocking scheme .
• Power consumption .
• Standardization is being addressed by the Virtual
  Socket Interface Alliance (VSIA)

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System on Chip interconnection

• AMBA (Advanced Microcontroller Bus Architecture)
  is a collection of buses from ARM for satisfying
  a range of different criteria.
• APB (Advanced Peripheral Bus) simple
  strobed-access bus with minimal interface
  complexity. Suitable for hosting peripherals.
• ASB (Advanced System Bus) a multimaster
  synchronous system bus.
• AHB (Advanced High Performance Bus) a high-
  throughput synchronous system backbone. Burst
  transfers and split transactions.

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System on Chip cores

• One solution to the design productivity gap is to
  make ASIC designs more standardized by reusing
  segments of previously manufactured chips.
• These segments are known as blocks, macros,
  cores or cells.
• The blocks can either be developed in-house or
  licensed from an IP company.
• Cores are the basic building blocks
• Voorbeeld de cc2430 zigbee chip.

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System on Chip cores

• Soft Macro
• Reusable synthesizable RTL or netlist of generic
  library elements
• User of the core is responsible for the
  implementation and layout
• Firm Macro
• Structurally and topologically optimized for
  performance and area through floor planning and
  placement
• Exist as synthesized code or as a netlist of
  generic library elements
• Hard Macro
• Reusable blocks optimized for performance, power,
  size and mapped to a specific process technology
• Exist as fully placed and routed netlist and as a
  fixed layout such as in GDSII format .

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GDSII
A rendering of a small GDSII standard cell with
three metal layers (dielectric has been removed).
The sand-colored structures are metal
interconnect, with the vertical pillars being
contacts, typically plugs of tungsten. The
reddish structures are polysilicon gates, and the
solid at the bottom is the crystalline silicon
bulk.
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System on Chip cores
Soft core
Reusability portability flexibility
Firm core
Hard core
Predictability, performance, time to market
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Cypress PSOC core
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System on Chip cores

• Locating the required cores and associated
  contract discussions can be a lengthy process
• Identification of IP vendors
• Evaluation criteria
• Comparative evaluation exercise
• Choice of core
• Contract negotiations
• Reuse restrictions
• Costs license, royalty, tool costs
• Core integration, simulation and verification

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The Benefits

• There are several benefits in integrating a large
  digital system into a single integrated circuit .
• These include
• Lower cost per gate .
• Lower power consumption .
• Faster circuit operation .
• More reliable implementation .
• Smaller physical size .
• Greater design security .

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The Drawbacks

• The principle drawbacks of SoC design are
  associated with the design pressures imposed on
  todays engineers , such as
• Time-to-market demands .
• Exponential fabrication cost .
• Increased verification requirements .
• Increased system complexity
• Design Gap

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Design gap
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Solution is Design Re-use

• Overcome complexity and verification issues by
  designing Intellectual Property (IP) to be
  re-usable .
• Done on such a scale that a new industry has been
  developed.
• Design activity is split into two groups
• IP Authors producers .
• IP Integrators consumers .
• IP Authors produce fully verified IP libraries
• Thus making overall verification task more
  manageable
• IP Integrators select, evaluate, integrate IP
  from multiple vendors
• IP integrated onto Integration Platform designed
  with specific application in mind

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Major SoC Applications

• Speech Signal Processing .
• Image and Video Signal Processing .
• Information Technologies
• PC interface (USB, PCI,PCI-Express, IDE,..etc)
  Computer peripheries (printer control, LCD
  monitor controller, DVD controller,.etc) .
• Data Communication
• Wireline Communication 10/100 Based-T, xDSL,
  Gigabit Ethernet,.. Etc
• Wireless communication BlueTooth, WLAN,
  2G/3G/4G, WiMax, UWB, ,etc
• Atmel CAP

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ATMEL Custemizable Atmel Processors

• The advantages of this design approach are
  six-fold
• Risk is reduced since the ARM core and
  peripherals (over 70 of the design) are fully
  verified in silicon, the designer does not have
  to worry about any of the ARM design aspects
  that work is already done.
• Design time is reduced since the SoC portion of
  the design is complete and the designer only has
  to focus on the portion of logic that would
  otherwise be in an FPGA. This logic is captured
  in the Metal Programmable (MP) Block of the CAP
  device.
• The CAP cycle time for place route and
  prototype fabrication is extremely short. Place
  route is limited to the metal layers of the MP
  block and the ROM personalization layer
  everything else is fixed. Fabrication time for
  prototypes is reduced since wafers are staged at
  the metal layers awaiting the Metal Programmable
  logic and ROM code from the designer. This cuts
  the fab cycle time in half.
• Design cost savings CAP NRE cost is
  significantly lower than that for standard cell
  ASICs. The total design cost for an ARM-based SoC
  using CAP technology is a fraction of that for a
  standard-cell equivalent, thanks to re-use of
  hardware/software functional blocks, reduced
  place route effort and the smaller number of
  masks.
• Low unit cost In volume, CAP costs only slightly
  more than an equivalent standard cell ASIC, and
  much less than an MCU FPGA combination for the
  same functionality.
• The CAP Emulation Board, industry-standard
  software development tools, device drivers,
  operating systems and extensive re-usable
  software modules facilitate software development,
  and enable hardware and software development to
  proceed in parallel.

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Starterkit zeer aantrekkelijk

• CPU CoreARM7TDMI
• Clock Speed (MHz)80
• On-chip SRAM (Kbytes)160
• MP Block Usable Gates
• FPGA InterfaceROM (Kbytes)
• 256NAND Flash Controller
• SDRAM Controller
• Static Memory Controller
• AHB Masters 2
• AHB Slaves 4
• Interrupts 14
• DPRAM2 Blocks 2Kx16
• USB Device (Full Speed) 6 endpointsSystem
• Peripheral DMA ChannelsClock

• Klantspecifieke logica
• Prijs 10 dollar bij afname van 10.000 stuks
• Klantspecifieke IP in silicon rond een standaard
  uC platform
• Zeer goedkoop start platform Cap-7
• Arm7 cylone II EP2C8F256C7N voor 399,-

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AMBA

• Staat voor Advanced Microcontroller Bus
  Architecture
• Deze standaard definieert de bus specificaties
  voor de communicatie tussen high speed on-chip
  componenten
• Drie verschillende bussen zijn gedefinieerd in de
  AMBA specificaties
• de Advanced High-performance Bus (AHB)
• de Advanced System Bus (ASB)
• de Advanced Peripheral Bus (APB).

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ARM7
On die Ram
External Bus Interface
AHB of ASB
Bridge
DMA Controller
APB
UART

• AMBA Advanced Microcontroller Bus Architectuur
• 3 belangrijke kenmerken AMBA protocol
• Timing aspecten van de bus zijn niet vastgelegd
• Busspanningen zijn niet vastgelegd
• Chip protocol onafhankelijk

Parallel I/O
Timer
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De AHB

• Staat voor Advanced High-performance Bus
• De AHB is te verdelen in 4 logische elementen
• AHB master
• AHB slave
• AHB arbitter
• AHB decoder

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De AHB

• Staat voor Advanced High-performance Bus
• De AHB is te verdelen in 4 logische elementen
• AHB master
• AHB slave
• AHB arbitter
• AHB decoder

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De AHB

• Staat voor Advanced High-performance Bus
• De AHB is te verdelen in 4 logische elementen
• AHB master
• AHB slave
• AHB arbitter
• AHB decoder

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De AHB

• Staat voor Advanced High-performance Bus
• De AHB is te verdelen in 4 logische elementen
• AHB master
• AHB slave
• AHB arbitter
• AHB decoder

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Kenmerken AHB

• Meerdere busmasters. De basis van het nieuwe
  concept!
• Gemultiplexte bus. Oplossing voor meerdere
  busmasters
• Regulering door een arbiter.
• Pipelined and burst mode transfer
• Split transactions
• Een slaafje met een lange response tijd kan
  tijdens het decoderen van de opdracht de bus
  loslaten en een ander proces laten passeren.
  Hierna is het tijd voor het eerste slaafje als
  hij zijn werkje klaar heeft.
• single clock edge operation
• Heel handig wanneer je timing analyse aan de gang
  gaat. Hiermee is het mogelijk om je ontwerp te
  controleren en te verifiëren
• non-tristate implementation
• Gebruik van een centrale gemultiplexte bus (zie
  plaatje volgende sheet)
• Variable busbreedte 16-,32-,(standaard in ARM
  ASB) maar ook 64,128 bits

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Pipelining within a burst
Address and data of consecutive transfers are
transmitted in same clock cycle,
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Wait cycles
Slave may not be ready to service
request. Inserts Wait cycle(s) by de-asserting
HREADY
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AHB busstructuur
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De ASB

• Staat voor Advanced System Bus
• De ASB is te verdelen in 4 logische elementen
• ASB master
• ASB slave
• ASB arbiter
• ASB decoder

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De ASB

• Staat voor Advanced System Bus
• De ASB is te verdelen in 4 logische elementen
• ASB master
• ASB slave
• ASB arbiter
• ASB decoder

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De ASB

• Staat voor Advanced System Bus
• De ASB is te verdelen in 4 logische elementen
• ASB master
• ASB slave
• ASB arbiter
• ASB decoder

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De ASB

• Staat voor Advanced System Bus
• De ASB is te verdelen in 4 logische elementen
• ASB master
• ASB slave
• ASB arbiter
• ASB decoder

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Kenmerken ASB

• Meerdere busmasters
• Regulering door een arbiter
• Pipelined operation
• Burst datatransfer
• Kent 3 typen transfers
• (sequential, nonsequential en address only)

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Kenmerken APB

• Is geoptimaliseerd voor minimale vermogenopname
• Vereenvoudigde opbouw van het businterface
• Relatieve lage bandbreedte t.o.v. de AHB of ASB
• Geen Pipelined operations
• Nieuwste versie APB relateert alle operaties
  t.o.v. de opgaande flank
• Lage belasting AHB of ASB door toepassing van een
  APB bridge

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Bus Conclusie

• AHB gebruiken we als systeembus wanneer een hoge
  bandbreedte vereist is tussen de macrocellen en
  de ARM processor
• ASB is de systeembus voor de midrange
  toepassingen of de oudere ARM processors
• APB is een aparte bus die men gebruikt als
  interface naar peripherals met een lage
  bandbreedte welke geen gebruiken maken van
  pipelining