Processor for WBASN

1
A System-On-Chip for Wireless Body Area Sensor
Network Node
Z. Stamenkovic, G. Panic, and G. Schoof
4. Results
3. Implementation

• VHDL model including verification environment
  (testbenches)
• In-house developed simulation, synthesis and
  layout generation scripts
• Verilog simulation models of hard SRAM blocks
• Each SRAM block includes BIST logic
• Logic synthesis using IHPs standard cell library
• Layout generated for IHPs 0.25 µm CMOS
  technology
• Verification via simulation
• Compiled test program loaded through I2C debug
  interface

• Chip area of 9 mm2
• 500 000 transistors
• 45 signal ports
• 24 power ports
• 5 BIST ports
• Extremely low power consumption of 0.06 mW/MHz
• Maximum processor frequency of 20 MHz having
  memories operating at 40 MHz

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